Program ICT for the UUT

Estimated reading time: 9 minutes

The goal of in-circuit test is to ensure that the PCB is operational and ready for system assembly, i.e., the integrity of all units under test connections, components and functional circuits on the board must be checked.

By Dennis Lia

In-circuit testing (ICT) generally is not a problem for common components such as resistors and capacitors. This is because most ICT units feature test routines that use the value and tolerance found on the schematic. But what is the test engineer to do if his tester has no such routine for a component and, in addition, the exact operational characteristic and tolerances of the part are indeterminate, e.g., when they are dictated by the combination of associated components?

One approach is for the tester* to "learn" unit under test (UUT) characteristics and limits. This involves writing a test routine that generates a set of input conditions, measures the output responses for known good boards (KGB), and calculates and saves the test limits for use in production test.

Programming the ICTThe ICT engineer usually is not given the functional performance specifications of all circuits on a printed circuit board (PCB) to be verified before passing it on to system assembly. In many cases, determining the performance is not a straightforward process and may even require a rigorous design analysis to determine test-limit values. Nevertheless, the engineer would prefer to test as much of the board's functionality as possible using a minimum of information and analysis.

The ICT can be programmed to learn the functional characteristics of any circuit that can be measured, and through this process, establish minimum and maximum test limits from KGBs. This procedure is especially useful for complicated analog and mixed-signal circuits for which design test limits are unavailable or extremely complicated to calculate.

Figure 1. UUT test models include a typical ICT with hard-coded limits (a), and one featuring a test-limits file and learn mode (b).

Figure 1a shows the typical all-in-one model for testing UUTs. It incorporates fixed limits hard-coded into the source files obtained from data sheet specifications or circuit analysis. Figure 1b shows the same test but with the ability to read from a UUT test-limits file, plus a learn mode that calculates new limits based on combining the "new-and-save" results. The model then writes the new limits for the UUT test-limits file.

To implement, the test engineer adds the ability to read the UUT test limits from a file, and when in the Learn mode, performs a limits-updating calculation based on the new data and saves it in the file.

Exploring the ConceptThe basis for this discussion is a specially developed hybrid test model that performs a spectral analysis of a low-pass-filter circuit. However, instead of requiring the engineer to know and specify the roll-off characteristic test limits, before the act of test generation, the model "learns" these data.

Having to specify the roll-off limits would lead to an awkward debugging process. For example, when the limits are changed, the test program must be regenerated and recompiled. Without the learn capability, the limits applied to each of the frequency elements of the high-pass-filter circuit must be reprogrammed into the test to match the filter's frequency-response characteristic, generally a prohibitively time-consuming task. The advantage of the learning model is that it can be used to test a high-pass-filter circuit over the same basic frequency range without change.

What if the circuit is not a high/low-pass filter? Or if the frequency response has a profile that defies understanding? Three options are available: 1) develop a new model for each special filter characteristic type, 2) do not test the filter functionally, or 3) develop a model that measures frequency response multiple times in a learn mode; computes the mean and standard deviation for each frequency element; and save new limits based on those statistics in a file for each filter circuit on the board. This would permit any filter circuit, with any characteristic, to have its frequency response learned by the same program.

To make the model's applicability as broad as possible, in this example, the multitone capabilities of the Arbitrary Waveform Generator (AWG) are stretched to the limit, creating a waveform with 30 frequency elements spaced logarithmically over a three-decade frequency range, from 25 Hz to 25 kHz, in a single tone, which essentially covers the full audio spectrum. The goal is to create a test model with a learn mode that is reliable and flexible, and to demonstrate this through a rigorous test case that exposes real-life test requirements.

Learn ModeThe process demonstrated here calls for the user to approve the results for a specified number of learned KGBs. It relies on the tester to display the frequency response of each learned UUT, together with limits, based on all of the previously learned devices (Figure 2). The example shows the tester's screens in the learn mode before saving the 31st UUT for the HY2 device on the demo board. The display shows the current UUT frequency response (for comparison to the learned average response), the new standard deviation and the new learned maximum/minimum limits.

Figure 2. Display of the frequency responses, with limits, of each learned UUT compared to the average. Shown are the new standard deviation and new learned maximum/minimum limits.

Using this method, very complex results can be displayed and quickly determined to be valid or invalid. Invalid results, from bad devices or bad connections, are not to be included in the calculation of the tabulated minimum/maximum limits. If the frequency response appears to be normal, the user responds with a "Y" and the limits data file is updated; if an "N," the file is unchanged. This process could be made more sophisticated by using statistics to automatically base the acceptance of the learned data. But this step would add another level of complexity that, for this evaluation, was not implemented.

Figure 3. The result of the test development is a two-terminal hybrid test model wherein an input multi-tone signal is generated with 30 frequency elements of equal amplitude between 25 Hz and 25 kHz (a). Output amplitude is measured for each frequency element by a DMM (b).

The test development results in the two-terminal hybrid test model are shown in Figure 3a. An input multitone signal is generated by the AWG with 30 frequency elements of equal amplitude between 25 Hz and 25 kHz. The output amplitude is measured for each frequency element by a digital multimeter, as shown in the block diagram (Figure 3b).

Figure 4. AWG plotting of the generated frequencies on a linear scale shows a logarithmic distribution over 25 Hz to 25 kHz.

Plotting the FrequenciesThe actual plot of the generated frequencies on a linear scale shows their logarithmic distribution over the three decades of full audio range, 25 Hz to 25 kHz (Figure 4). By default, 10 frequency elements are logarithmically spread out in each decade, giving equal coverage throughout the entire range. The diagram is a waveform display of the multitone audio path input frequency spectrum showing the logarithmic spacing of the 30 frequencies. The X-axis is in units of 25 Hz; point 1,000 is equal to 25 Hz x 1,000 = 25 kHz. Viewing the actual input- and output-frequency elements on a logarithmic scale, each appears evenly spaced and is easier to discern visually (Figure 5). The Y-axis is logarithmic: the roll-off of the circuit smoothly drops until it approaches 200 μV, after which it levels off in a jittery fashion. Here it consists of the noise floor of the test system (~100 μV) plus harmonic distortion because of the multitone construction and the circuit under test. The classic way to look at frequency response is in terms of decibels (dB) with respect to a reference level. In this case, the reference level can be defined as the highest value (0.1 V) while each frequency-element amplitude in dB can be calculated with respect to that level. Finally, to test the frequency response of this circuit, a maximum and minimum limit for each frequency element may be specified as shown. It may be adequate to use a fixed ±dB value at each frequency element or, as in the case above, smaller at one end and larger at the other.

Figure 5. Screen of the actual input- and output-frequency elements on a logarithmic scale clearly shows even spacing.

A more sophisticated test might use statistics to determine the limits. To do this, the device must be tested numerous times and the mean and standard deviations calculated; from this a set of minimum and maximum limits for the test could be figured. A reasonable limit might be a mean value ±3 as standard deviation. The diagram in Figure 6 shows the filter with the ±3 standard deviation limits applied. A correction is applied at any point where the measured voltage level is at or below the noise floor (100 μV). The minimum limit is set to an arbitrarily low value so as not to fail devices for an output value below the noise floor.

Figure 6. After testing a device several times, the mean and standard deviations are calculated to derive a set of minimum/maximum limits, here ±3.

Implementing the TesterTo implement so that an automatic tester can learn the device characteristics, a UUT test-limits data file must be created. For simplicity and readability, each line at the beginning of the file contains a string description ending with an equals sign. White space and then the value to be read and saved by the test program follow. The table of frequency elements that the program uses to save and update as the device is being learned is more (but scarcely) complicated. In the test mode, the typical time required to read the UUT test-limits file from disk was approximately 50 ms, which is relatively insignificant compared to the UUT test time (~1.25 seconds). The sidebar describes the UUT test-limits file and its derivation.

ConclusionDeveloping tests having the capability to learn the UUT test limits is feasible provided that the tester language supports reading and writing strings and floating point values to a file.

The choice of data-file format remains with the programmer and can include options that can be changed between tests without regenerating and recompiling the test program. This can be very convenient for such options as changing the test flow, conditions and limits without changing the program. Once developed, a test model with the ability to learn the UUT test limits can be used to test a class of devices with similar characteristics. As in this case, the model developed could be used to test other types of filters over the same 25 Hz to 25 kHz range with no change to the test model required.

The demonstration described is a rather complex example. The concept can be applied to any component to be tested. For example, if a test model for a 1NXXX zener diode were unavailable, one could write a model to measure and learn the zener voltage, resulting in a model that could be used to test almost any zener diode. The concept can be applied to any device whose characteristics can be measured but whose specification limits are unknown.

Contact the author for examples of test language for determining if a test-limits file exists for a specific UUT or how to create one.

• GenRad 228X ICT.

DENNIS LIA, senior software engineer, may be contacted at GenRad Inc., 7 Technology Park Drive, Westford, MA 01886; (978) 589-7272; Fax: (978) 589-7007; E-mail: liad@genrad.com; Internet: www.genrad.com.