Mitigation of Pure Tin Risk by Tin-Lead SMT Reflow – Results of an Industry Round-Robin

Estimated reading time: 2 minutes

Abstract

The risk associated with whisker growth from pure tin solderable terminations is fully mitigated when all of the pure tin is dissolved into tin-lead solder during SMT reflow. In order to take full advantage of this phenomenon, it is necessary to understand the conditions under which such coverage can be assured. A round robin study has been performed by IPC Task group 8-81f, during which identical sets of test vehicles were assembled at multiple locations, in accordance with IPC J-STD-001, Class 3. All of the test vehicles were analyzed to determine the extent of complete tin dissolution on a variety of component types. Results of this study are presented together with relevant conclusions and recommendations to guide high-reliability end-users on the applicability and limitations of this mitigation strategy.

Background

Manufacturers of high reliability electronics have been working for many years to mitigate the deleterious effects of tin whisker formation. One highly effective means to suppress the growth of tin whiskers is to replace the pure tin plating with reflowed tin lead solder. (This approach is only available to manufacturers whose products are not subject to RoHS.) One approach to achieve total replacement of tin with tin lead solder is to perform a special hot solder dip process on the piece parts prior to assembly. Another approach is to fully consume the tin plating by tin lead solder during the SMT reflow process that occurs during circuit card assembly. This phenomenon of tin replacement during SMT reflow has been termed “self-mitigation,” because the components mitigate by themselves without the need of any special additional processing. Self-mitigation has many advantages over other forms of tin mitigation because it is: highly effective, adds no additional cost, and subjects the components to no additional handling.

The principal challenge to implementing self-mitigation as a standard practice is lack of confidence in the conditions under which components will reliably self-mitigate. Prior work concluded that for a specific set of process conditions, board finish, and pad design, self-mitigation can be predicted by the geometry of the component terminations^[1]. It is not clear, however, how these results apply for different manufacturing processes, board finishes, and pad sizes. Without this understanding, the only reliable means for systems integrators to be confident that self-mitigation has been achieved on a given set of assemblies is to duplicate the conditions of the prior study, or to perform direct measurements on the as-received hardware.

The existence of this knowledge gap prompted the Pb-free Electronics Risk Management Council (PERM, IPC Committee 8-81) to initiate a project in 2014 under IPC task group 8-81F, to perform a study. The first phase of that study has been completed, and this report describes that study and the results to date.

Design of Experiment

The task team agreed to perform a new set of experiments involving the manufacture of identical sets of test vehicles at a number of different locations, all assembled to the requirements of IPC J-STD 001, Class 3. For simplicity, and to permit direct comparison with the results of the prior study, it was decided to use the same board layout and components from the prior study. Many potential factors for inclusion in the DOE were considered.

To read this entire article, which appeared in the September 2016 issue of SMT Magazine, click here.