Final Finishes: Taking Gold Thickness into Account

Estimated reading time: 9 minutes

Martin Bunce was one of several people from MacDermid Enthone who presented at SMTA International this year. He sat down with me for a chat about his paper on final finishes, particularly with regard to controlling gold thickness.

Patty Goldman: Martin, please tell me a bit about yourself.

Martin Bunce: I work for MacDermid Enthone and I’m the global application manager for the final finish business. I've been in the role for the last two years.

I joined the PCB industry straight from university in '96 with LeaRonal in the UK. I joined MacDermid 15 years ago and have held various technical positions in Europe before moving to America nearly six years ago, to join MacDermid Enthone’s Global Group. I’m now based in the Global Development Center in Waterbury, Connecticut.

Goldman: You presented a paper here on final finishes, I believe. Tell me about that.

Bunce: For the last five years, the IPC 4-14 Plating Processes subcommittee has been working to improve IPC-4552A Performance Specification for Electroless Nickel/Immersion Gold (ENIG) Plating for Printed Boards, and revision A has just been released in September. It's going to raise the quality bar for the ENIG deposit but also create a few challenges for the PCB fabricators in the way that they manufacture. My paper focused on what has changed in the specification revision, the associated challenges that the PCB fabricators will be facing, and how to overcome these challenges and manufacture ENIG to this improved standard.

Goldman: Can you give me a few specifics on the challenges?

Bunce: The whole specification has been developed to avoid corrosion-related soldering defects, including several key changes to Revision A to minimize this risk. The first significant change is the introduction of XRF measurement capability analysis in the form of a Type 1 Gage Study, and options to cope with non-conforming tools to ensure ENIG product meets specification. If we cannot measure gold thickness accurately, how can we control thickness in production? Once we are happy that we have a good gold thickness measurement capability, there is a new gold thickness specification to meet. The previous 4552 specification had a minimum gold thickness requirement of 1.97 μin, and no maximum.  The revision specifies a new minimum of 1.58 μin, and for the first time, a maximum of 3.94 μin. The idea behind this change is to reduce the amount of electroless nickel corrosion that occurs when forcing higher gold thickness.

The next important change is that the PCB fabricator will need to demonstrate that the ENIG process is producing electroless nickel phosphorous content to the chemical supplier’s recommendations. Low phosphorous content reduces the electroless nickel deposit’s corrosion resistance and is therefore prone to increased corrosion. There are errors involved in phosphorous content measurement systems that need to be understood; the paper discusses mitigation tactics.

The last significant change is introduction of acceptability levels for electroless nickel corrosion and a detailed section on evaluation techniques. This section will shed light on a traditionally grey area of ENIG quality and hopefully bring some clarity to a much-debated subject of what is acceptable.

Goldman: Yes, we've heard some of these things from others on the subcommittee over the years.

Bunce: During the mid-1990s when black pad was first starting to be observed and root causation was not understood, it was worrying times for the ENIG finish. Subsequent research has really improved understanding of the failure mechanism, and ENIG process reliability has significantly improved the robustness of the finish with newer chemical formulations. However, people who are still around from the mid ‘90s still remember the pain and fear of “black pad.”

Immersion gold deposition relies on a controlled corrosion (galvanic displacement reaction) of the electroless nickel deposit, thus some “corrosion” is expected and normal. However, corrosion acceptability was always a gray area. Historically, an ENIG solderability failure always found an area of some corrosion that automatically became the root cause of the failure; a lot of time has been spent on corrosion discussion between PCB fab quality departments, assemblers and ENIG chemistry suppliers, which prevented a quicker determination of the true root cause of the soldering defect. The IPC subcommittee has now revamped the 4552 specification and it's going to give everyone a lot more awareness of corrosion acceptability and how to monitor and control within acceptable limits in production. 

One of the biggest challenges the IPC-4552 Revision A will bring to PCB fabrication is demonstration of acceptable ENIG corrosion based on the 3-level system introduced in the specification. Increased measurement and observation will undoubtedly mean more time and cost for some PCB fabricators who currently do not monitor corrosion.

Goldman: You've been working on this standard for how long?

Bunce: The IPC-4552A standard development has been going on for about five years.

During the integration of former MacDermid with Enthone and OMG Electronic Materials businesses, my role was to review the legacy ENIG processes available from the three companies and work with the newly combined research team to put together our leading technology to meet the ENIG market needs. We seem to be in a unique position because we've been doing all this activity to make sure we've got the best ENIG process available from our legacy businesses in parallel to the 4-14 plating committee working to define the improved standard. So, the developing IPC guidelines became our benchmark to make sure that the resultant ENIG process exceeds requirements. We've not only eliminated the corrosion discussion by consistently giving level one IPC corrosion, but we've also worked to improve the gold thickness control and distribution on different sized pads. Our marketing team has coined the phrase “every pad, every day, every shift (is the same).”

Goldman: You mentioned that you felt this was going to be a problem for PCB shops. Is it because they can't control those thicknesses or because they can’t measure it?

Bunce: First, we need to ensure we have a good gold thickness measurement system before we even consider working to the new specification. A Type 1 gauge study is now required to demonstrate a PCB fabricator can make repeatable measurements. If gauge capability analysis finds that an x-ray fluorescence (XRF) machine to be non-conforming [Cg > 1.33 is required for IPC-4552A] this can result in an increase in the number of XRF readings needed during production to ensure accurate gold thickness measurements are obtained. In some cases, we have evaluated recently, we have found that XRF capability of gold measurement (to 4552A) increased the XRF analysis time enough to create a bottleneck that was not workable in production. In this case a reduced specification tolerance should be implemented, which puts further strain on the ENIG process to deliver consistent gold thickness.

This is all discussed in the paper, but the short story is, if we can minimize the measurement system variation, it gives us more room in this new specification for the process variation. It's going to be a challenge, but correct ENIG process selection and process control methodology can help to work with reduced gold thickness tolerances if required. Secondly, if we talk about the new gold thickness specification, in the previous 4552 document we only had a lower specification limit. It's like driving a car around a post; it’s very easy.

Goldman: You could say, "Ah, leave it in the bath a little longer to be sure."

Bunce: If we leave the PCB in the immersion gold chemistry for longer to ensure we don’t have low gold thickness, this increases the amount of electroless nickel corrosion, because there is more time for the galvanic displacement reaction to proceed and more nickel dissolution into the immersion gold chemistry. The addition of an upper specification limit means we must fit our process data in between two posts without hitting either. This can be further complicated if XRF capability dictates a further reduction in the specification tolerance.

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