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SMT Solver: Dealing With Package Parasitics

Packaging technology has constantly evolved over the decades from through-hole package to SMT with ever-decreasing pitches. There are many factors that play a role in the selection of a package, such as their cost and physical size, but the role package parasitics play in package selection has not changed over many decades. For example, while the silicon designer is preoccupied with performance issues in picoseconds, the system designer is still struggling with performance issues in nanoseconds. This 1000X reduction in performance is caused by packages that house the silicon commonly referred to as package parasitics, and they are very different in various types of packages. 
 
Package parasitics are those undesired lead (outside the package) and bond wires (inside the package) inductance and capacitance that get in the way of the electrons trying to get to their destinations fast. Electrons are a hurried bunch and like to travel at the speed of light. But they are being slowed by package parasitics. Why do we need to deal with packages, especially if they act like a parasite? Can’t we just get rid of those packages? Why bother with parasites?
 
To answer this question, we need to ask the next logical question: What do these packages do besides behave like parasites? They do some very useful things. For example, the packages provide power to the silicon so that the electrons can move around. These electrons are always in a hurry, and their fast movement generates lots of heat. The packages make it possible to dissipate and remove that heat so that the electrons can continue to move around at high speed. If the heat is not dissipated adequately, the higher junction temperature (temperature of silicon) will slow the electrons down. In a way, the packages make it possible to speed things up. 
 
This is not all the good things that the packages do. They also make it possible to interconnect the signals of all the silicon on the board so that the electrons can all talk to each other. Last, but not least, they provide a safe shelter to the silicon. Being homeless is no fun for the silicon, especially if the environment around it is full of humidity and heat. A balanced way to think about a package may be that even though they slow the electrons down because of the capacitance and inductance of their leads and wire bonds, the packages also provide useful functions, such as powering, interconnecting, and shelter for the safety and comfort of its inhabitant—the silicon inside. 
 
Despite the good things the packages do, many designers are trying to get rid of them anyway because they don’t like any degradation in silicon’s performance. One can get rid of the package by using bare silicon. Bare silicon is generally used as chip-on-board (COB) or flip-chip. There are some real differences in these terms. The COB term is used when the silicon is either wire bonded to the board directly or is used in the form of tape-automated bonding (TAB). However, chip and wire and TAB add wire-bond inductance. The highest performance is achieved when the bare silicon is directly flipped over and bonded to the underlying substrate. No wire bonds or leads are involved in the flip-chip process. 
 
One can achieve higher performance with bare chips when using them as chip and wire or flip-chip, but you create one major new problem. We should note that in addition to the package functions mentioned earlier, the packages also allow the pretesting of silicon before being soldered to the board. Out of all the multiple chips on the board, it takes only one bad silicon to render the entire assembly worthless. To correct the problem, you have to remove and replace the bad silicon, but reworking bare silicon on a substrate is not a piece of cake. On the other hand, if the silicon is housed in a package, the test sockets, and the whole burn-in and test infrastructure, are in place to enable the use of only functional silicon. 
 
This issue of not being able to test bare silicon is referred to as a “known good die” (KGD) problem. It is not easy to test a bare die, although the industry has made good progress in this area. If that silicon is housed in a package (or used as a TAB device), the problem of using bad silicon does not arise. If you insist on using the bare silicon to achieve the performance you need, you can use flip-chip but must be willing to pay a higher cost in terms of more rejects due to a KGD problem. It is possible to achieve better performance if one is willing to pay a higher cost. There are certainly applications where it is worthwhile to pay a higher cost to achieve the needed performance, but it is generally in niche applications, such as multichip modules (MCM). 
 
The solution for the industry may not be necessary for getting rid of the package but developing more efficient packages that can perform the traditional function of the package of protecting, powering, interconnecting, and providing a KGD without a significant penalty in performance. However, if you look at the R&D budget and effort on package versus silicon, there is no comparison. All the dollars are going into silicon development. We need that progress in silicon technology, but you cannot achieve the highest performance with a poor package. While we may not be able to get rid of package parasitics entirely, we are on the constant hunt for minimizing package parasitics when we transition from through-hole to SMT, fine-pitch, ball-grid array (BGA), chip-scale package (CSP), bottom-terminated component (BTC), and bare or flip-chip with no package at all with the inherent pros and cons of each of these packages.
 
The next level of interconnect that is slowing the silicon’s performance is the interconnect substrate. The traditional and widely used substrate fabrication technology cannot accommodate fine lines and microvias needed for interconnecting high pin count and lower pitch packages (or silicon). While package technology has not made the comparable progress achieved in the silicon technology over the last decade, the substrate technology is in the horse and buggy days compared to package technology. Unless the industry makes comparable progress in substrate and package technologies, the desire to achieve that performance in picoseconds will remain only a dream. 
 
There are a variety of packages with their advantages and disadvantages. The key distinguishing feature in them is their pitch, the way the pins are arranged, and the type of housing material used (plastic or ceramic).

This column originally appeared in the February issue of SMT007 Magazine.