Mentor’s User2User Conference Focuses on Semiconductor Development

Estimated reading time: 7 minutes

Mentor conducted its annual User2User Conference virtually this year on November 10. In a departure from past U2U conferences, this event was focused primarily on developing semiconductor advances.

The conference started with a short keynote from Kevin Hiroshima, VP of sales for the West. After the normal greetings, noting that attendance was double that of the in-person conference and sharing his regrets for having to be virtual, Kevin hoped that this U2U conference would be easier “than teaching math to your 9-year-old.” He pointed out the contributions of Siemens to the design and thermal distribution simulation of the camera instruments and electrical distribution system for the new orbiting astronomical observatory, the James Webb Space Telescope, which will orbit 1.5 million kilometers above the earth.

Kevin then introduced the main keynote speaker, Joe Sawicki, the executive VP for Mentor IC EDA. Joe said the COVID-19 pandemic has accelerated the “digitization of everything,” or in Siemen’s focus, from verification to validation to digital twin.

Joe noted that during this pandemic, there was an exponential growth of data and storage—nearly 400X growth! There has been a 92% CAGR of data traffic; enabled by 5G, this will continue to 2030 with nearly 392,540 exabytes annually. The pandemic has exploded the demand for collaboration of every sort. Business applications tools have the following growth from February to June 2020:

• Microsoft Teams: 894%
• Zoom: 677%
• WebEx: 451%
• GoToMeeting: 398%
• Slack: 395%
• Skype for Business: 179%

All of these challenges demand that we adopt new ways of getting our job done. Joe concentrated on the next-generation of systems, including AI.

Marc Andreesen’s famous quote, “Software is eating the world,” is certainly coming true. For Siemens, this is impacting all products and applications. The challenges like that of the autonomous vehicle are impacting all aspects of product development. Joe emphasized that key requirements are changing daily under our feet. Systems and software complexities are driving verification and validation of electronics integration.

In addition to 100 billion device integrated circuits for SOC methodologies, four areas stand out:

1. SOC design: Using custom accelerators for performance as well as software and energy management.
2. Verification: The complexity is driving verification challenges, especially software, where Mentor has the Veloce HW emulator to enable verification while the chip is still being designed.
3. Validation: Custom testing and the Veloce emulator are available to complete this job in parallel.
4. Monitoring (In-Life): Once the device is in production and distribution, IoT allows constant monitoring of its performance.

The digital twin is a constant ingredient in this effort. Joe concluded his keynote with the hope that the breakout sessions would provide the answers to many of these questions.

Seven out of nine breakout sessions covered semiconductor advances. The sessions available were:

1. Analog Mixed-Signal Verification
2. Custom/Analog Design, MEMS, and Silicon Photonics
3. Design-for-Test Operations and Embedded Analysis
4. Functional Verification
5. HW-Assisted Verification and Validation
6. High-Density Advanced Packaging Design and Verification
7. High-Level Synthesis/Verification and Power Estimation/Optimization
8. IC Implementation, Physical Verification, Circuit Verification, and DFM
9. PCB System Design

I chose to attend the high-density advanced packaging sessions.

Jan Vardaman of TechSearch International gave the first presentation, “Enabling AI Hardware: What Is the Role for Advanced Packaging?”

Jan’s company has been doing market research, identifying trends, tracking innovations, and analyzing growth on semiconductor packaging for the last 40 years, and she is an expert on the subject. She selected AI as a good candidate to illustrate all the complexities that can go into the next generation of packaging challenges, as AI is being studied everywhere, from medical diagnostics and predictive analysis to IC fab yield improvements and autonomous vehicles.

The current high-end in packaging is the heterogeneous integration of devices on the silicon interposer:

1. This is logic (FPGA, GPU, or ASIC) on the silicon interposer with TSVs to handle the connection to the HBM stack. Stacks consist of 4-8 DRAM to 12 assorted types of RAM. This is common to Xilinx, NVIDIA, TSMC, and others. The silicon interposer is expensive but has L/S capability down to 0.4/0.4 microns and in packages up to 100 mm x 100 mm with thousands of I/Os.
2. Another example is the silicon bridge that enables multiple chips to relate to an Si interposer connecting bumps on the die’s edge for localized high-density interconnections. At IBM, these direct bonded heterogeneous devices are then C4 bonded to organic packages.
3. With fan-out on substrates (Si, glass, or organics), these RDLs have 2/2-micron L/S with very fine pitch and thousands of I/Os. Examples are Intel’s Foveros, ASE’s FOCoS, TSMC’s InFO, Samsung’s RDL, Tongfu’s FOPoS, and Amkor’s SWIFT.

The use of “performance glass” and new organic materials to lower costs and increase size is growing.

The next presentation, “Packaging Technology Innovations for Our Transforming World,” was delivered by Rick Rice, the senior VP of marketing for the ASE Group. ASE Group is a major design and fabricator of advanced packaging, and Rick described the new challenges of implementing heterogeneous integration now that chiplets are available. With past MCMs with bare die, the challenge was “verification for known good bare dies.” But with chiplets and new chip I/O standards, advanced packaging can extend Moore’s Law by implementing SoCs at a lower cost and with faster time-to-market. Advanced packaging can be the new level of interconnects by:

• Moving die partitioning from SoC to packaging level modularity
• HIP provides near and more than monolithic integration with better performance than SoC and at a low cost.
• IP reuse and new EDA tools provide yield improvement, lower costs, and rapid implementation

The new information supplied by assembly design kits (ADK) from fabricators provide designers with:

• Multi-die chiplets layout capabilities to support all chiplet attach methods
• Enable flexible connectivity models and automatic routing styles across integration levels
• Provide DFA and DFM checking and flows
• Support new EDA tools system verification and validation (DRC, LLVS, SI/PI, and mechanical simulation/modeling

Rich concluded with a simple example of “Integrating Design Into Manufacturing,” of course, using Mentor Xpedition-HDAP.

The third of the four presentations was “Design of Chip-Package-Board Daisy Chains With Xpedition Package Designer,” by Senior Global Packaging Engineer Kendall Hines. This is the new EDA tool Mentor has created to support this growing area of electronic interconnections.

His presentation addressed the complexity of creating test vehicles and using daisy chains on them when there is a multitude of different components and methods of interconnections. Test vehicles are the starting point to solve this interconnect puzzle but must have the physical characteristics of the target design. In addition, the test vehicle must verify and test all the various mechanical connections (CTE, soldering ability, bump/ball pitch, wire bonding, copper pillars, etc.) of the target design and still be able to visualize and track interconnects across the subsystem.

Kendall provided a demonstration, using Xpedition to design a complex interposer on organic materials by importing the die bump design and then the printed circuit SMT land design. Assigning net names and routing the daisy chain to emulate the target interposer can be considerably more complex than just interconnecting land patterns in normal PCB designs. Finally, adding documentation to assist in the assembly and testing the resulting test vehicle.

The last presentation in this session was by Ruben Fuentes, VP of design for Amkor Technologies, one of the largest and most experienced IC packaging fabricators. His presentation, “Design Process and Methodology for Achieving High-Volume Production Quality for SWIFT (HDFO) Packaging,” focused on their ADK.

Ruben explained the need for and the implementation of a more advanced ADK set of software. Called a SmartPackage PADK, this one is specifically designed for Mentor’s Xpedition HDAP EDA tool to bridge the gap between the design, manufacturing, and assembly of WLPs. Set up to achieve the equilibrium of design-to-manufacturing by the creation of a new set of specifications to define design parameters for SWIFT^R(HDFO) that aligns with Amkor’s manufacturing and assembly processes.

The new PADK is a series of data files and scripts developed to support wafer-level packaging (WLP) on dies. It provides for each process configuration and technology variant used by foundries. This ensures that the new substrate meets Amkor’s design, manufacturing, test, and assembly requirements by providing real-time verification to minimize design cycle time and quickly evaluate manufacturing and assembly violations. Hopefully, this will reduce cycle time and limit the number of design iterations required. This is a great idea that would offer PCB designers greater DFA capabilities.

Conclusion
Advanced printed circuit design is entering a new phase. Heterogeneous Integration Design (HID) is the new term for it. The packaging layer for chips is now expanding to be a new layer of complex component interconnections. This is supported by Mentor establishing a new version of Xpedition-HDAP for high-density advanced packaging.

The difference between the traditional Xpedition and the HDAP version lies in its ability to bring in IC designs and its associated data, including new materials not currently used for printed circuits. This is not Gerber or IPC-2581 data but for semiconductor standards and its associated data. This new level of interconnect is growing both in applications and size. Some of the largest substrates are 100 mm x 100 mm and are produced in large panels. For those printed circuit designers interested in “moving up the chain,” this new level offers challenges, rewards, and opportunities.