Cadence Expands Collaboration with Samsung Foundry to Advance 3D-IC Design
October 18, 2022 | Cadence Design Systems, Inc.Estimated reading time: 1 minute
Cadence Design Systems, Inc., a collaborative partner in the Samsung Advanced Foundry Ecosystem (SAFE), announced that it has expanded its collaboration with Samsung Foundry to accelerate 3D-IC design. Through the continued collaboration, the reference flow featuring the Cadence Integrity 3D-IC platform has been enabled to advance Samsung Foundry’s 3D-IC methodology. Using the Cadence platform, customers creating complex, next-generation hyperscale computing, mobile, automotive and AI applications can greatly optimize power, performance and area (PPA) for each die.
The PPA of a design can be impacted when chips are stacked in a 3D-IC configuration versus a 2D configuration due to the presence of large 3D structures like TSVs, which connect the stacked chips. In addition to blocking standard cell placement area, these structures block routing resources as well. The Cadence Integrity 3D-IC platform alleviates these traditional challenges, letting users create multiple TSV insertion scenarios and devise an optimal 3D structure placement on a die with reduced wirelength penalties while boosting PPA and productivity. The platform also lets users perform 3D-IC design planning, implementation and signoff from a single cockpit, making the design process faster and easier.
“Customers creating stacked die designs at advanced nodes are always looking to make use of the benefits of our technologies without compromising PPA,” said SangYun Kim, vice president of the Foundry Design Technology Team at Samsung Electronics. “The enablement that resulted from our collaboration with Cadence leverages advanced 3D-IC capabilities that provide our mutual customers with innovative techniques to build 3D designs without giving up PPA due to the additional structures introduced with multi-die stacking. After working with Cadence successfully on the 3D-IC system planning reference flow, we are confident our customers can achieve their own unique design goals for multi-die stacked designs.”
“Through our latest collaboration with Samsung Foundry, we’re enabling customers to circumvent the typical challenges that arise with 3D-IC design while optimizing PPA in parallel,” said Vivek Mishra, corporate vice president of the Digital and Signoff Group at Cadence. “The Integrity 3D-IC platform brings together leadingsilicon and package implementation with system analysiscapabilities, helping designers improve overall productivity. By leveraging Samsung Foundry’s advanced 3D-IC capabilities and the Integrity 3D-IC platform, our customers have access to an optimal solution for high-quality, multi-die implementation.”
Suggested Items
Indium Corporation to Showcase HIA Materials at ECTC
05/07/2024 | Indium CorporationAs an industry leader in innovative materials solutions for semiconductor packaging and assembly, Indium Corporation® will feature its advanced products designed to meet the evolving challenges of heterogeneous integration and assembly (HIA) and fine-pitch system-in-package (SiP) applications at the 74th Electronic Components and Technology Conference (ECTC), May 28‒31, in Denver, Colorado.
Siemens Delivers New Solido IP Validation Suite
05/07/2024 | SiemensSiemens Digital Industries Software introduced Solido™ IP Validation Suite software, a comprehensive, automated signoff solution for quality assurance across all design intellectual property (IP) types, including standard cells, memories and IP blocks.
Altair Acquires Research in Flight, Forging a New Path for Aerodynamic Analysis
05/07/2024 | AltairAltair a global leader in computational intelligence, announced it has acquired Research in Flight, maker of FlightStream®, which provides computational fluid dynamics (CFD) software with a large footprint in the aerospace and defense sector and a growing presence in marine, energy, turbomachinery, and automotive applications.
Happy’s Tech Talk #28: The Power Mesh Architecture for PCBs
05/07/2024 | Happy Holden -- Column: Happy’s Tech TalkA significant decrease in HDI substrate production cost can be achieved by reducing the number of substrate layers from conventional through-hole multilayers and microvia multilayers of eight, 10, 12 (and more), down to four. Besides reducing direct processing steps, yield will increase as defect producing operations are eliminated.
Hirose Launches Solution Partner Network to Address Changing Design Challenges
05/06/2024 | HiroseHirose, a leader in the design and manufacturing of innovative connector solutions, has established a Solution Partner Network that enables OEMs to quickly explore product design, specialty IP, and component fulfillment options that best suit their needs.