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Wafer-Level Packaging Symposium Program Announced
December 13, 2023 | SMTAEstimated reading time: Less than a minute
The SMTA is excited to announce the technical program for the Wafer-Level Packaging Symposium. The symposium will be held February 13-15, 2024 at The Hyatt Regency San Francisco Airport in San Francisco, California.
The technical program includes over 25 expert speakers who delve into wafer-level packaging advances, 3D wafer-level integration, advanced packaging inspection, materials innovation, fan-out wafer-level packaging and manufacturing excellence. The program features presentations from leading companies including Intel Corporation, KLA Corporation, Department of Defense, and more.
Additionally, the technical program features two keynote presentations. On Tuesday, February 13, 2024, Manish Dubey, Ph.D., AMD, will present, “Advanced Packaging: Key Enabler for AI.” On Wednesday, February 14, 2024, Benjamin S. Cook, Meta, will present, “Wafer-Level Fan Out Technology Options to Realize High-Performance AI Enabled Augmented Reality (AR) Wearable Devices.”
The symposium will culminate with two professional development courses on Thursday, February 15, 2024. The first course, “Polymers for Wafer-Level Packaging,” will be instructed by Jeff Gotro, Ph.D., InnoCentrix, LLC, from 8:30 am – 12:00 pm (PST). Tom Dory, Ph.D., Fujifilm Electronic Materials, will instruct the second course, “Package Assembly Processes and Technology,” from 1:00 pm – 4:30 pm (PST). Access to the courses is included in standard registration.
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