EIPC 2025 Winter Conference, Day 1: From Manufacturing to Sustainability

Estimated reading time: 12 minutes

The EIPC 2025 Winter Conference, Feb. 4-5, in Luxembourg City, featured keynotes and two days conference proceedings. This is my report of the first day’s conference proceedings. The keynote session and second-day conference proceedings are reported separately.

The first technical session was introduced and moderated by Thomas Michels, CEO of ILFA in Germany. The theme of the session was “Requirements for manufacturability of today’s and future PCBs,” and his first speaker was Martyn Gaudion, sales and marketing director of Polar Instruments.

Well-known as a gifted speaker with a talent for making complex topics intelligible and understandable (and even enjoyable), Gaudion’s presentation explored some of the realities of stackup and signal integrity as conventional multilayer builds approach the dimensions of ultra-high-density interconnect (UHDI).

He observed that although 75 microns may have been considered a practical limit for PCB traces fabricated by traditional subtractive manufacturing processes, semi-additive and modified semi-additive technologies, together with the use of thinner base foils or electroless copper base layers, are now enabling a trend to the finer lines demanded by UHDI designs.

Typical attributes of traces produced by semi-additive processing include precise line-width control and near-vertical sidewalls. Combined with tighter spacing, these can be expected to result in more consistent impedance control and better signal integrity, but some additional factors have to be taken into account when using time-domain reflectometry (TDR) to measure their electrical characteristics.

Commenting that the goal of designer and fabricator is to ensure the most accurate correlation between the design and fabricated impedance, Gaudion discussed enhanced techniques and improvements in impedance correlation on fine-line PCB traces, using the example of an edge-coupled offset stripline. He emphasised the impact of DC resistance on TDR measurement, significant on traces finer than 100 microns, whereas on wider traces it was safe to dismiss its effect. He mentioned launch-point extrapolation and DC resistance compensation as two valid methods for de-embedding the DC resistance from a TDR trace.

Besides trace widths and spacings, it is important to consider layer-to-layer separations in UHDI designs. Separations less than 20 microns approach the skin depth of the signal, so that inductance might start to change with frequency. Polar is examining the implications of measurement and modelling correlation, as well as continuing to address the challenges presented by new materials and new stack concepts.

Gaudion’s presentation examined some of the issues involved in measuring the electrical characteristics of PCBs produced by additive processing, so it seemed logical to learn of some of the challenges of actually making leading-edge fine-line PCBs in production. Dr. Tamara Aderneuer, application engineer at Dyconex in Switzerland, gave us some insight.

The general trend for increased functionality and smaller size is driving the requirement for high-density interconnections, and precisely-defined trace edges are necessary for efficient signal transmission in high-frequency and high-speed communications.

Aderneuer demonstrated how a design with 70-micron pads at 100-micron pitch can theoretically be routed with 5-micron lines and spaces to enable two tracks between pads, and indicated the limitations of subtractive processing compared with mSAP, ASAP, and SAP semi-additive techniques. She showed actual examples of structures with lines/spaces of 12/15 microns, 8/12 microns, and 7/10 microns made using SAP technology.

But these ultra-fine structures present challenges in inspection, where there is a need for higher resolution than can be achieved with standard equipment. Similarly, higher-resolution photolithography equipment is required in manufacturing, as well as advanced requirements on quality, thickness, and precision of materials. Yields in production are critically affected by the impact of particulate contamination on highly fragile fine-line structures.

Dyconex has made substantial investment in high-resolution LDI imaging and AOI inspection equipment, together with optimised clean-room facilities, as well as careful machine alignment throughout the process chain. All this, in conjunction with their expertise in engineering, optimisation of process parameters, and minimisation of handling contributed to achieving high yields in manufacture, enabling the company to support an increasing customer demand for fine-line PCB production with additive technology.

Design for manufacturing was the subject of the presentation by Christophe Lotz, CEO of Aster Technologies in France, who discussed how the new challenges of electronics will impact DFM.

His company had developed a software platform that enabled printed circuit boards and assemblies, along with assembly and test equipment, to be modelled in a virtual environment, providing digital continuity from design to production and allowing industrial design rules to be applied to the digital twin so that areas of concern could be addressed before the physical build of the product. By employing digital twin technology, the need for prototyping is reduced, improving time-to-market and boosting productivity.

There are typically four main categories of engineer using the system in their specific software suites: PCB design, PCB design validation, PCB manufacture, and PCB assembly. Although the principles are universally applicable, key markets are in mission-critical, safety-critical, and high-complexity sectors.

Lotz discussed different dimensions of DFM in design-rule checking, design for manufacturing, design for assembly, and design for test, emphasising that the associated constraints must be applied from the very beginning of the design, although he commented that the DFM market is highly fragmented, with little or no digital continuity, and that many manufacturers still process files without any automation.

As electronics evolves, with more complex designs and manufacturing and additional economic constraints, the challenges to DFM has increased. To aid design rule checking, Lotz recommended that conductor routing be consistent with standard industrial parameters and he advocated compliance with the IEC/PASS AFNOR 2212 specification, created by the French standardisation association, as a practical guide offering designers and manufacturers a modern framework tailored to their needs.

The second technical session was introduced and moderated by Jean-Claude Roth, technical director at CCI Eurolam in France. The theme of the session was “Advanced innovations in PCB manufacturing.”

“Misregistration is one of the major reasons for poor yield in the PCB manufacturing process,” said Andre Bodegom, managing director of Adeon Technologies in the Netherlands, in his opening statement. He described a range of solutions addressing the challenges of registration control by predicting inner-layer scale factors and optimising drill and outer-layer registration.

He explained that misregistration is a complex issue that can result from a combination of distortions arising from many factors associated with PCB manufacture: materials, processes, environment, and design. The effects of distortion and their impact on registration are driven by the technology of the product.

He listed examples of additional registration challenges associated with new materials having no production history, increased product density giving less registration tolerance per process, sequential build up resulting in more processes to register, quick turn, and low volume product that must be right the first time with no opportunity for pilot lots.

Traditional methods of registration control have typically generated lots of data but with limited understanding or analysis. But the data presently available from pre-CAM, CAM, and manufacturing processes can be turned into knowledge and used by a self-learning prediction engine as “predictive intelligence” to generate scale factors that can dramatically improve registration and hence improve yield and profitability.

Bodegom demonstrated how design data, stack-up data, and measurement data is fed into a predictive modelling database as a continuous measure-learn-predict self-improvement cycle. He illustrated how the system addresses such tasks as best-fit drill optimisation and compensation for material grain-direction effects, and how it can be seamlessly integrated and interfaced with an enormous range of proprietary and industry-standard equipment and software.

The system has advanced measurement analysis capabilities and provides real time reporting for managers and engineers.

Bodegom also discussed the benefits of 3D data analysis and virtual cross-sections compared with traditional destructive micro-sectioning. He concluded his comprehensive presentation with an illustration of an integrated predictive system for total registration control in a smart manufacturing context.

An innovative method for trimming of multilayer panels after lamination was discussed by Milena Fritz, CEO of SAT Electronic in Germany.

Traditional flash-trimming methods tended to generate dust and leave rough edges with a risk of local delamination. The technique she described is a development of v-scoring and produces a clean-cut beveled edge while the dust is efficiently removed by a pin-point collection system. 

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