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Trouble in Your Tank: In Complex Systems, Design Rules Aren’t Optional

There is no question that the electronics industry, especially in circuit board design and fabrication, advanced packaging, and innovation throughout the value chain, has seen a significant transformation, whether it be in materials, system architecture, HDI and ultra HDI, semiconductors, or chiplets. AI and high-performance computing (HPC) are driving change across several fronts, including material properties, assembly techniques (think hybrid bonding), and power management. Innovation has triggered the need for a better understanding of:

• Higher power on smaller traces
• Signal integrity and magnetic effects at higher frequencies
• New processing technologies (dielectric film, semi- and fully additive)
• Optical materials
• Innovation in cooling techniques

The silicon-to-systems approach must not be taken lightly. Essentially, winging it to make this all work, because our collective experiences show us the way, reminds me of the song that says, “Party like it’s 1999.” Well, it’s not 1999, or 2023, for that matter. So much has changed in rapid-fire succession as Moore’s Law has reached its limits, and chiplets and larger format substrates are becoming the norm. All this, however, comes with its own set of circumstances. Regardless, let’s look at things from a rulebook perspective, without negating opportunities for innovation.

Rulebooks and Design Rules
With the increasing complexity of electronic systems, it is more critical than ever to ensure close cooperation among the end user, the designer, the fabricators, and the teams assembling these packages. You see multiple chips mounted onto a silicon interposer, the interposer soldered to a substrate, and the entire package assembled onto a board. All this has to function as the device/system was intended. What does all this mean? First, even with this level of complexity and need for higher performance, you must be able to fabricate these packages with high yield. More than one executive in this industry has said, “It’s all about yields.”

Design for excellence (DFX) requires a set of rules and cooperation between all parties in the project. Since many of these projects involve several companies (one firm handling the board/substrate design, another the interposer, another the fab of the board and substrate), it is easy for things to get lost in translation.

I have watched designs handed to the fabricator with significant flaws, whether they concern material selection and signal integrity, lines and spaces too fine for the fabricator to succeed, or stacked microvias without understanding the potential for microvia interfacial fracture (MVIA).

If there were no set rules, the process would be a free-for-all. Designers often break these rules in the name of efficiency and optimum electrical performance. This often leads to product failure and multiple and costly respins.

That’s why design rules (and understanding each party’s constraints) are parameters that, when followed, will ensure an accurate design. It requires checking the design process step by step with all parties involved: fabricators, assembly, and the silicon fab for the interposer. It includes electrical rule checks (ERC) for the schematic and design rule checks (DRC) for the PCB and substrate. These rules serve a specific purpose. Think of them as gates that one must pass prior to moving to the next step. For example, the designer works with data to create a schematic. Once that is completed, ERC checks are required to validate whether the design is electrically correct. The ERC needs to give a clean report. If there is anything off, stop and fix the issue right away, as they can’t be fixed later in the process.

When designers were pushing the software to deliver the most efficient design, was there a discussion with the board and substrate fabricators about whether the design could be manufactured reliably? Perhaps the OEM has communicated in the Statement of Work that the entire package (Z-axis) can only be so high, including the substrate thickness, the height of the chip or chips on the interposer, the interposer-to-substrate distance, the protective lid for the package, and the thickness added by the solder. Imagine if the designers completed the tedious task of routing signals, designing the stackup, providing the drill file, etc., only to learn that the substrate as designed is too thick to fit in the socket on the product board.

This is precisely why the designer must be cognizant of the constraints up front before going too deep into the design process. The fabricator and assembly firm should be involved from the outset. 

A Few Caveats
If the rules are not set or are set incorrectly, you should at least understand how the board/substrate package will be used. Is this a package for AI, or an ultra HDI design for very high-frequency applications? Is it needed for high-power? The design rules will differ depending on what the circuit is supposed to do.

It’s important that issues arising early in the design phase not be ignored. Signal integrity models, for example, can predict signal loss at various frequencies. What if the modeling shows issues with overshoot and undershoot? Address it immediately, not when the design is transferred to the fabricator for manufacturing.

Finally, check the design rules at each step and follow them throughout the design process. This will save heartache later.

Finally, don’t underestimate the need for constant communication and collaboration with all parties involved, including the OEM, the EMS provider, PCB fabricator, and the substrate and chips/interposer teams. I cannot stress the need for transparency enough, and for the parties involved in the fabrication process to communicate their manufacturing capabilities and constraints to the design team. There are no trade-offs here.

This column originally appeared in the April 2026 issue of I-Connect007 Magazine.