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The Bleeding Edge: Engineering Low CTE Boards

The first requirement for engineering low coefficient of thermal expansion (CTE) printed circuit boards is to understand the physics behind the properties of CTE. One must know what creates problems and how to engineer methods to minimize the CTE effect on printed circuits.

CTE simply means that every material in the world expands or contracts as its temperature changes. The expansion is expressed in ppm/°C or parts per million per °C. For example, Fr4 typically has a CTE of 22 ppm/°c or 0.000022 inches expansion per °C. This expansion has a second property, called Young's Modulus, defined as how hard a material pushes when it expands.

One example is the difference in how steel and fiberglass expands. If we clamp a hunk of steel in a vice and heat the steel, it will expand or push with so much force, it can break the vice. If we put the same size fiberglass hunk in the vice and heat the fiberglass to the same temperature, it will not push as hard and, therefore, will not break the vice. Fiber glass has a lower Young's Modulus so it pushes less as it tries to expand. The Young's Modulus of steel is 40 mpsi and fiberglass measures 2.5 mpsi.

Another example: If we take a sheet of copper invar copper (CIC) and a sheet of Rogers Teflon, the CIC will change dimensions with a force of 21 mpsi--the Teflon will expand with a force of only 1.6 mpsi. If we laminate the materials together and measure the CTE, the number will be much closer to the CTE of the copper invar then the low Young's Modulus of Teflon. To calculate the effect of two materials on final CTE, we use a sum equation--adding up the mass of each layer and the Young's Modulus.

Most printed circuits will have materials with different CTEs sandwiched together with components of different CTE's soldered on board. When temperature excursions occur, due to changes in either ambient conditions or the power dissipated by the circuit, these materials will expand differently, leading to the creation of stresses. In severe cases, we may see warping of an entire board or a solder joint fracture of the components.

CTE is very important in circuits that mount large BGA chip packages due to the shearing of the solder balls. The stresses created as the circuit board expands at a different rate than the ceramic BGA package can literally tear off a chip package. Silicon's very small CTE means that if we directly mount silicon chips to a PCB, the  larger CTE of the board will crack the fragile silicon as its dimensions changes and the silicon chip does not.

The CTE and Young's Modulus numbers of materials can be engineered and used to an advantage when we try to lower the CTE of a circuit board to match silicon. We can start with a low CTE core, such as thermount^TM or CCI--this will limit how much the circuit card will expand with heat. CIC has a CTE of 8.4 and a Young's Modulus of 21 mpsi. If we use normal Fr4 prepreg for the remainder of the circuit, the high Young's Modulus of the Fr4 will affect the CCI. If, however, we use lower Young's Modulus materials, such as Rogers4000 series or dielectric films, will result in a lower overall CTE number.

In the case of the large ceramic chip carrier with a CTE 5.6 ppm/°C, which is mounted on a conventional Fr4 printed circuit board at a CTE 17 ppm/°C, the mismatch in thermal expansion will cause shear stresses within the solder that mounts the chip carrier. After a sufficient number of thermal cycles, the stress will eventually lead to work hardening of the solder, which results in cracking of the solder joint itself. The resulting intermittent electrical conductivity is unacceptable in today's high reliability electronics applications.

The expansion of materials is volumetric in nature, however the restraint in the laminate construction is in-plane, which means along the length of the PCB, not the thickness. As all materials expand with CTE in a volumetric fashion, because we restrained the laminate in the X-Y direction, the Z axis will expand. Reinforcing fabrics used in laminates glass, quartz and Kevlar® have lower coefficients of thermal expansion than the resin and high modulus values. Glass is 12 mpsi, Kevlar® is higher at 19 mpsi, which restrain the in-plane expansion of the PCB. The Z-direction coefficient of thermal expansion increases faster, above the glass transition temperature of the resin system by as much as four times. In a typical PCB, this means the Z axis increases from 50 to 200 ppm/°C at the Tg temperature.

The final CTE will depend on such properties as the modulus of each of the components of the PCB, the effectiveness bond of the laminates to one another, the degree of transfer of the modulus of the stiffer materials into the resin and the volume ratio of one material to another in the PCB. A typical multilayer PCB has a CTE of 16-18 ppm/°C. A specially designed low CTE PCB can be as low as 5-6 ppm.

Another approach is to use a low expansion controlling layer like CIC within the structure of the printed wiring board whose high modulus will dominate the expansion and reduce the effective CTE of the package.

Other composite foils and metal layers may be used, such as copper clad molybdenum, which has better Z direction heat transfer than copper-invar-copper and lower CTE numbers.

The CIC layers constrain expansion and serve as power and ground planes. It is felt by some that distributed thin CIC planes near the surface of the board may have as much effect on CTE control as a single much thicker central core. Their copper content makes them good electrical conductors. The 0.006" foil is not a good thermal conductor because there is too little mass of copper--its main purpose is to provide expansion control.

Designers can use thicker CIC pieces for thermal management or the higher thermal material CMC (i.e as a heat sink) in addition to CTE control.

A constraining core to control in-plane expansion is designed into many PWBs intended primarily for surface mounting of BGA , leadless chip carriers and direct die mounting. The basic requirements for a constraining core are that it must have a low CTE in the X-Y plane of the board and that it must also have a sufficiently high modulus to prevent the rest of the board from expanding at its typical rate of 14-18 ppm/°C.

Other mechanical properties of a constraining core, such as heat transfer, electrical conductivity and weight, are as important as the processing characteristics, such as ability to be drilled, copper-plated, etched and bonded to other PCB materials. The use of a metal core with low CTE in the middle of a PWB is designed to solve the problem of chip attachment, yet, many times, the manufacturing problems over shadow the advantage.

The main problem is the lack of reliability when bonding together two materials with very different CTE's. The laminate part of the board, still wants to move at 18 ppm/°C and the CIC at 5.5 ppm/°C. This creates large shear forces between the two, which, quite often, results in delamination of the board at the CIC junction. A combination of high modulus low CTE core, with low modulus outer layers, helps solve the shear problem, because the low modulus material will give little resistance to the low CTE core in expansion and reduce shear forces.

We consider that the use of aramid fiber reinforced PWBs the best way available to achieve a low CTE PCBs. The high fiber modulus of the Kevlar®, combined with its negative X-Y coefficient of thermal expansion (-4 ppm/°C), gives this system the power to control in-plane CTE when low modulus dielectrics are used.

Kevlar® laminates feature low CTEs which are made in a range from 4-8 ppm/°C. Kevlar® is also exceptionally light in weight, with much lower density (1.44) than conventional E-glass (2.54). They also have lower dielectric constant (3.6) than E-glass (4.5), which results in higher signal speeds.

To better control the flatness of multilayers, we can use our new thin film dielectric material as top layers, the film flows easily filling the top of the tracks while not transmitting any of the bumps.

By designing the multilayer with a low CTE, but high Young's Modulus cores, such copper invar copper, copper moly copper or carbon fiber, you create the power control layers. We then use low modulus laminate, such as Rogers 4350 or Sierra's new  thin film dielectric material, as low modulus layers for the circuits. The new method will lower the CTE of a multilayer by 5-7 ppm, typically a multilayer with copper invar copper and Kevlar (thermount) laminate will have a CTE of 9 to 12, where  the same multilayer  built with copper invar copper or thermount and Rogers4350 or thin film dielectric will have a CTE of 6-9.

Bob Tarzwell, Director of Technology at Sierra Proto Express, is working with Ken Bahl to introduce new bleeding edge, advanced circuit technology like lead-free, high reliable electronics, heat sinking technology and ultra fine lines to the world. Since selling his company in 2000, Bob has disseminated PCB high-tech to many companies as a consultant, and has written ten books on PCBs and car racing. He has three patent-pending applications in fine lines, high reliability and outer space PCBs. He is currently semi-retired in the Bahamas, spending his free time writing books, working on antique cars and deep sea fishing.

Ken Bahl, President of Sierra Proto Express (San Jose, California), started in the PCB business in 1965 as a process engineer with Honeywell in New Hampshire. In 1986, Ken founded Sierra Proto Express, the PCB industry's leader in innovative bleeding edge technologies-dedicated to producing Tomorrow's Technology Today.

For more information, visit http://www.protoexpress.com/. To contact the authors, click here.