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Optimizing Test Operations to Cut Costs
December 31, 1969 |Estimated reading time: 10 minutes
Contract manufacturers (CMs) operate on razor-thin margins, where cutting excess costs is a way of life. However, most CMs have standardized on expensive, traditional test equipment that locks them into high purchase, operating, and support costs. To remain profitable and competitive, CMs must optimize their test operations to match test equipment to today’s fault spectrum.
By John VanNewkirk
The economics of the contract manufacturing business closely resemble those of a supermarket: high-volume production at razor-thin margins. In this price-sensitive environment, CMs focus on minimizing cost wherever possible. Over the past decade, CMs have successfully attacked cost from virtually every angle. Strict supply-chain management has pared component and inventory costs. Consolidating capital-intensive manufacturing facilities and locating them in low-labor-cost regions has also helped margins.
There is one manufacturing expense category that CMs have failed to attack with the cost-cutting axe - circuit board test. This is surprising, considering that circuit board test typically represents 10-30% of assembly expense.1 Nevertheless, comprehensive belt-and-suspenders test strategies continue to focus on diagnosing fault classes that rarely occur. OEMs and CMs continue to use the same custom functional test setups they have always used. As production grows, test managers continue to buy traditional in-circuit testers (ICTs) with high operating costs, in the name of standardization. Test programs continue to be written using assumptions and tools dating back to the mid-1990s.
Because test is not a value-added manufacturing activity, it should be a cost-reduction target. However, CMs have little incentive to attack test cost because it is passed directly to the OEM customer as a non-recurring engineering (NRE) expense. More creative CMs make board test a profit center and pass along test costs with a substantial markup.
So why doesn’t the OEM customer demand lower testing costs? Invariably, the fear of under-testing, which could result in higher product failure rates, trumps cost-reduction initiatives. CMs are more than happy to ameliorate this fear by promising the OEM test comprehensiveness, and using sophisticated, complex, big-iron testers.
The Shifted Fault Spectrum
While board-test strategies have not changed much since the heyday of big-iron testers purchased in large quantities by CMs, component and manufacturing technologies have changed since then. Current consumer products are mostly digital and increasingly handheld. Shrinking form factors, smaller parts, denser boards, and higher integration have resulted in a radically altered distribution of manufacturing defects (the fault spectrum), compared to products of a few years ago.2
The fault spectrum has changed, but test strategies haven’t. The result is a substantial mismatch between the defects the tester is attempting to diagnose and the faults that actually exist on boards. Both real and opportunity costs of this mismatch are high. For example, digital defects on boards produced a few years ago could represent up to 35% of the fault spectrum, but now are typically measured at low parts-per-million (ppm) rates. Where digital vector test was once essential, it is now almost superfluous. However, around 50% of the cost of buying and using traditional big-iron ICTs stems from the hardware and software requirements surrounding digital-test capability.
Newer, low-cost ICTs that eliminate digital backdrive-vector capabilities are not only better-matched to today’s fault spectrum, they are available at a fraction of the acquisition and operating cost of traditional ICTs. Test managers often resist switching platforms, clinging instead to the idea of “tester standardization,” or a belief that OEMs will feel more comfortable knowing their products are tested on a traditional tester.
Nevertheless, several OEMs and CMs have actively reduced test costs by comparing the costs of operating a traditional tester to that of using a low-cost tester for the majority of their boards. By performing this analysis and switching to low-cost testers, they have been able to reduce test costs up to 40%. Just as important is shifting resources to test for new fault classes such as solder quality issues, which are increasingly critical in the age of the RoHS Directive. This may require investing in new technologies such as automated imaging.
A Test-cost Analysis Tool
Taking action requires understanding the root causes of test expense and the costs of alternative test strategies. However, in the typical production environment crises, most test managers have neither the time nor the tools to examine test costs closely.
A straightforward cost-analysis tool has been developed to simplify this task. Unlike most test-economics models that require users to measure and input a daunting number of precise variables, the test strategy cost comparison (TSCC) model encourages estimation and approximation. It directly compares the cost of alternative ICT strategies for a hypothetical PCB built in a given fault-spectrum environment.3 The model is designed specifically to compare the cost of using traditional ICT to the cost of deploying low-cost ICT.
The analysis process begins by estimating an average defect rate for a given assembly environment building a typical circuit board. Table 1 shows an estimated defect rate for each of five fault classes in a postulated SMT assembly process.4 Next, the analyst specifies parameters of a typical board in terms of component count, type, etc. The TSCC model then applies the average defect rates against the specifics of the typical board, resulting in a calculated fault spectrum (Table 2).
Fault classDefect rateUnitSolder quality defect rate90DPMOMechanical defect rate75PPMDigital IC defect rate35PPMParts failure rate50PPMAssembly process failure rate65DPMOThis model is based on estimated (or measured) defect rates for five fault classes.Table 1. Process defect rates for a SMT process.
Calculated fault spectrum(defects/1,000 boards)Solder quality41.0Mechanical quality22.5Digital IC2.1Parts defects15.0Process defects20.2Total defects/1,000 boards100.8Table 2. Calculated fault spectrum for boards built in Table 1.
Now that the fault spectrum has been calculated, the next step is to select test-coverage rates for each of the five fault categories in the fault spectrum for each ICT. In this example, we compare a traditional ICT that includes digital-vector-test capability to a low-cost ICT without such functionality. Therefore, the only test-coverage difference between the two testers is their digital IC fault-coverage capability. Because digital defects comprise just 2% of our example fault spectrum, results shown in Table 3 are not surprising. The two testers have essentially identical calculated test coverage - 57.3% for traditional ICT and 55.2% for low-cost ICT. These test-coverage values translate to nearly identical yields of 95.8% and 95.6%, respectively.
Assumed test coverage of fault spectrumTraditional ICT Low-cost ICTFault spectrum(defects/1,000 boards)ICT testcoverageRemaining defects/1,000 boardsICT Test CoverageRemaining defects/1,000 boardsSolder quality41.067%13.567%13.5Mechanical quality22.50%22.50%22.5Digital IC2.1100%0.00%2.1Parts defects15.080%3.080%3.0Process defects20.280%4.080%4.0Total defects/1,000 boards not detected at ICT 43.1 45.2Calculated ICT test coverage57.3% 55.2% Calculated yield after ICT* 95.78% 95.58%*Yield = e-D where D = defect rate exiting test.Table 3. Test coverage of the calculated fault spectrum.Economic Impact of Today’s Fault Spectrum
With just 20 basis points (0.2%) separating the two testers’ yields, the economic impact of using a traditional test strategy in an environment in which digital faults rarely occur comes into focus. Incorporating tester capital, operating and applications costs, and a variety of production variables, the model provides direct comparison of the annual projected costs of two alternative ICT test strategies for testing a typical board.
Let’s assume that 10 new typical board types are introduced each year into a production environment producing 1,000,000 boards per year.5 Assume that both testers take 30 seconds (including handling time) to test a single board, and that all labor rates associated with using and programming either tester are the same.6 At a production volume of 1,000,000 boards per year, a 30-second average board test time translates to a requirement of four test systems. Table 4 summarizes the costs of in-circuit alternatives.
Cost elementTraditional ICTLow-Cost ICT% DifferenceNumber of testers required @ 30 sec./board for 1,000,000 boards per year440%Annual tester acquisition cost (amortized over 5 years)$116,000$49,60057%Annual test system support cost (5% of capital cost/ year)$27,000$12,00056%Average cost per new test fixture$15,000$8,00047%Average cost per new test program$7,000$4,00043%Total annual cost for 10 new test jobs (fixtures and programs)$670,000$360,00056%Total annual test cost$813,000$421,60046%ICT cost per board (1,000,000 boards/year)$0.81$0.42 Table 4. Comparison of test-cost strategies of traditional and low-cost ICTs.
Calculated test costs using traditional ICT equal $0.81 per board, while low-cost ICT is 48% lower at $0.42 per board. While most test managers focus on capital acquisition costs when comparing ICT alternatives, it is worth noting that the largest cost savings lie in the substantial difference in test-job cost (test fixture cost plus programming cost multiplied by the number of test jobs introduced each year). This divergence of traditional and low-cost ICT costs shifts further as test-job variety and production volume increase.
The upshot of this example analysis is clear - the reality of today’s typical fault spectrum with few digital defects calls into question the economic desirability of continuing to use traditional ICT on every board type. Further, the risk profile of under-testing on a low-cost platform is no greater than on the traditional ICT, as the tester fault coverage and resulting test yield are almost identical.
Tester Portfolio Management
As this example demonstrates, rapid technological changes and the resulting mismatch between the fault spectrum and test strategy have created a significant opportunity to reduce test cost without affecting test coverage adversely. CMs who recognize this opportunity and act on it enjoy increased operating and competitive advantage. OEMs that recognize this opportunity and equip themselves with data are well-positioned to negotiate lower overall prices from their EMS provider.
There is a three-step path to test-cost reduction. The first step is marshalling the managerial will to view board test not as a sacrosanct activity - which can’t be tampered with because it might impact product quality and reliability adversely - but as a viable cost-reduction opportunity. Second, only by actually understanding existing test cost can progress be made to reduce it. The TSCC model is a useful tool. The most critical aspect of understanding is, “Know thy fault spectrum.”
The third step is to re-examine long-standing assumptions about the role of the ICT system. For more than 30 years, ICT has been a primary quality gate for electronics manufacturing. Even for today’s complex SMT circuit technology and the shifted fault spectrum, this will not change - ICT remains the most efficient way to detect most defect classes because it can diagnose electrical defects that are invisible to other technologies, such as automated imaging. However, the shifted fault spectrum impacts what type of ICT must be performed. This, in turn, affects the nature and cost of the ICT itself. The shifted fault spectrum usually means lowering ICT costs by jettisoning once-critical test capabilities.
Conclusion
Taking action to reduce ICT test costs does not require abandoning traditional ICT. Instead, it requires using them on board types in which their capability is absolutely necessary. Test engineers should seek the highest reasonable fault coverage for each new board that enters the test department. But they should do so on the lowest possible cost-test platform. As the cost-analysis example demonstrates, the benefit of this approach is that, by shifting as many test jobs as possible to low-cost ICT, managers reap the benefits of uncompromised test coverage and lower total operating, support, and overhead expenses.
REFERENCES
1 Assembly expense doesn’t include the cost of components or the circuit board itself.
2 Root causes of the shifted fault spectrum include:
- Defects due to bad components have decreased substantially, especially for digital ICs, resulting in digital IC-related defects becoming a smaller proportion of total defects.
- The highly automated SMT process produces fewer process defects in part placement than thru-hole processes. Process-related faults now comprise a smaller proportion of the overall fault spectrum.
- In SMT, solder-related connectivity problems occur more frequently than solder bridges (shorts).
- Most solder-related defects are latent or quality-related.
- Small connectors and tight physical tolerances result in mechanical defects becoming a greater percentage of the fault spectrum.
3 The test strategy cost comparison (TSCC) model evaluates the technical and economic aspects of two alternative ICT systems in a given production environment - producing a mix of boards over a variable economic time frame.
4 In an actual manufacturing environment, there are more than five defect categories, but the idea of the model is first-order approximation to avoid getting into too much detail.
5 At this throughput rate, assuming a single shift environment and a work year of 2,080 hours, the TSCC model predicts that four ICT testers (either traditional or low-cost) are required.
6 Includes multiple fixtures per test job. In this case, four test fixtures for each test job because there are four testers in use.
John VanNewkirk, CEO, CheckSum, may be contacted at (360) 435-5510; e-mail: john.vannewkirk@checksum.com.