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Mass Imaging Advances for Next-generation Assemblies
December 31, 1969 |Estimated reading time: 8 minutes
High-accuracy mass imaging of electronics materials continues to advance in response to manufacturing challenges brought about by advanced packaging, next-generation SMT assembly and approaching lead-free deadlines.
By Richard Heimsch
Making advanced electronics products pervasive while addressing concerns, such as environmental effects of materials, energy consumption and basic business priorities is a challenge. Manufacturing techniques and equipment cannot answer these issues, but eliminating lead and other harmful substances from electronics assemblies, and building components and end-products that consume less energy while operating is within their scope.
Creating and assembling advanced semiconductor packages using flip chip and chip-scale packaging are significant challenges facing the electronics manufacturing community. Lead-free assembly also is changing established process behaviors and parameters, and is driving a range of changes in manufacturing technology.
In SMT assembly, mass imaging must meet demands for greater accuracy, while increasing repeatability and process control in next-generation packages. These include fine-pitch and chip-scale packages, as well as miniaturized passive components such as the 01005 outlines. In addition to traditional markets, SMT assembly also faces an opportunity to enhance the efficiency and productivity of material deposition processes for advanced semiconductor packages. These include wafer bumping, solder ball attach, underfilling, transfer molding and lid sealing, as well as a number of other processes at wafer, substrate and package levels.
Semiconductor Packaging
Although the semiconductor industry established methods for creating area interconnect arrays for flip chip and chip-scale packages, these relied on traditional approaches to managing and depositing materials such as solder balls. Applying mass imaging techniques will improve throughput and assembly cost for each package, while being based on tried technology familiar to SMT assemblers. Further benefits include the ability to easily create an automated process flow, to reduce the factory floor real estate required to perform each process, and reduce machine stoppages and assist rates, downtime and capital expenditure by using more straightforward and robust equipment and processes.
High-accuracy mass imaging for component package assembly also unlocks the door for SMT assemblers to move upstream, building packages themselves before assembling them directly onto the board. Furthermore, it reduces the barriers to entry for specialist, non-captive packaging start-ups, bringing new ideas into the marketplace. Many semiconductor OEMs also are implementing mass imaging to gain throughput, yield and cost advantages over competitors.
Mass imaging platforms are emerging to meet advanced package-assembly challenges; and are turning to linear drives and next-generation positional encoders to enhance alignment accuracy and repeatability for wafer-level processes. The current benchmark is accuracy and repeatability to 2 Cpk at ±12.5 µm, which needs to be achieved while driving the total cycle time below 7 seconds to maximize throughput advantages available from mass imaging.
Following accurate alignment to wafer-level resolution, stencil properties influence the accuracy of the subsequent imaging phase. Electro-formed stencil technology can deliver the resolution required to create area grid arrays directly on the wafer, while creating chip-scale DRAM packages. In addition to superior resolution, the material properties of these nickel stencils allow paste to release efficiently from apertures. Combined with consistent aperture filling using enhanced enclosed-head printing technologies, this ensures high-paste-transfer efficiency, which is critical to wafer bumping where low-paste volumes are deposited. Low-volume derivatives of the enclosed print head originally developed for SMT imaging also are more manageable and reduce waste when performing wafer-level processes.
Mass imaging platforms now entering service at OEM and EMS sites are more than motion-enhanced screen printers. Equipment designers have re-engineered external interfaces to meet JEDEC standards and de-facto standards such as Auer boats commonly used to transport singulated substrates between automated processes. For example, compatibility with the Front Opening Unified Pod (FOUP), as well as wafer carriers and cassettes for wafer sizes up to 300 mm, allows these machines to become an integrated part of a highly automated assembly process.
Virtual panel tooling (VPT) has emerged in substrate-level processes to solve the challenges of handling and aligning multiple singulated substrates. VPT uses a precision pin design and a matched vacuum tower that centers each substrate within a JEDEC-compliant carrier before lifting them into printing position. The effect is that of a virtual panel consisting of up to 60 independently aligned substrates. VPT is designed for direct fitting to the machine’s tooling bed, which may be identical to standard SMT tooling beds.
These advances in motion control, handling interfaces, tooling and stencil design are enabling mass imaging platforms to reach greater resolution and repeatability, addressing the majority of material deposition challenges from wafer level to final molding. Combined with natural flexibility, cost-efficiency and robustness, semiconductor package-assembly methods and processes can allow high-volume products to benefit from the advantages of advanced packages.
Dominating SMT, One Generation Ahead
Widespread adoption of flip chip technology means that board-level assembly requires the same precision as package-assembly processes. At the high-end, the same motion control and material metering developments that are proving essential for semiconductor packaging also will reach SMT assembly markets. Assemblers adopting 0201 passives in large numbers will appreciate additional accuracy afforded by these semiconductor-inspired technologies; and will find it essential as 01005 outlines further emerge.
Meeting the global demand for consumer products requires more speed to minimize tact time. Linear motors, driven at maximum possible speed with minimal vibration, help minimize alignment and excursion time of the transfer head. But challenging established principles behind actions such as post-print inspection could accelerate wider aspects of the process. Replacing traditional quantitative post-print inspection with a faster verification routine that returns a simple go/no-go result allows 100% screening of printed boards without imposing a time penalty. These systems quickly tell operators what they need to know about each board, and isolate boards with printing errors before additional assembly operations are performed.
Lead-free Realities
When considering accuracy, throughput and handling challenges posed by next-generation SMT assembly and advanced packaging, manufacturers also must be prepared for the transition to lead-free. Reflow has been focused on as the main process step requiring modification, but it is becoming clear that existing print processes also will need to adapt to new materials. For example, wetting forces are lower, which means that paste-on-pad accuracy must improve because the deposit can no longer be expected to center itself from surface tension under existing design rules. The high intrinsic value of the new pastes, which have higher tin content, as well as silver and copper as part of the solder alloy, also makes material management and waste reduction essential to the bottom line. Established enclosed print-head technologies reduce waste while enhancing aperture filling compared to traditional squeegee methodology (Figure 1).
Figure 1. New variants of enclosed transfer heads are among key enabling technologies.
Further avenues for experimentation include analyzing current stencil-design rules in relation to lead-free process performance. New design rules, as well as different stencil alloys, appear to hold the keys to countering reduced transfer efficiency of lead-free pastes. Research shows that transfer efficiency also depends on separation speed, so machine control software may need to adapt to allow engineers to optimize lead-free processes.
Process Support Technologies
Regardless of the application - semiconductor packaging or SMT assembly - modern processes are required to operate at optimal efficiency for extended periods with negligible assists or unplanned stoppages. Setup requirements often are complex, but there also is less time to train operators, for example, to use new enclosed-head variants or recover from an error in a new and complex process. Process support techniques also are changing, and platforms must adapt to make the most of these changes.
Broadband communications and the increasing scope of IP-based telecom services open the door to several machine and process-support innovations. Operators can access information in rich and informative formats such as graphical or multimedia demonstrations and tutorials. It also is possible for a service-control center to exercise sophisticated machine modes to perform diagnostics or demonstrate a complex procedure. Other possibilities include SMS messaging direct an operator’s cellular handset, alerting the user when consumables need to be replenished.
Figure 2. Operators need to be able to control extensive management and help functions without moving away from machines.
Emerging platforms are adapting to support sophisticated communications between the machine, the operator and the vendor’s support infrastructure. These infrastructures include staffed service-control centers and online knowledge servers that let operators access information over the Internet (Figure 2). In turn, vendor service control centers need more detailed information from their base of installed machines to offer services that will add value to customers’ businesses while trimming operating costs. Optimizing maintenance schedules, monitoring trends, predicting failures and planning corrective action at the next scheduled service visit are some of the value-add services possible when the machine infrastructure delivers the necessary information to the service-control center.
To enable this, electrical control infrastructures are moving away from the simple wiring loom, and moving toward a field bus implementation supporting control, address and data signals. One such infrastructure, intelligent scalable control area network (ISCAN) provides an efficient way to deliver control signals to machine subsystems and collects extensive status data as the machine operates. Storing this data using standard CANbus protocols builds a repository of information that can be used to trigger automatic alerts and help create a direct and optimal machine-maintenance schedule.
Figure 3. New-user interfaces support expanded platform functionality.
Other developments include new-user interfaces that can deliver content-rich support information, as well as basic machine control information (Figure 3). In one such system, the user interface acts as the front-end for a package of new features including broadband wireless connectivity to the Internet, with embedded security and encryption technologies. As a result, many emerging mass imaging platforms are equipped to exploit new IP-based services as the scope and diversity of IP communications increases.
Conclusion
By rapidly developing to penetrate advanced chip-scale packaging markets, high-accuracy mass imaging technologies also have evolved to address the next-generation speed and accuracy SMT demands. However, it is the close coupling of these features with innovative new approaches to equipment and process support that hold the key to long-term success for equipment owners. Emerging mass imaging platforms (Figure 4) put immense power on factory floors and allow operators to use that power to the fullest advantage.
Figure 4. This platform uses advanced features for area array packaging.
Richard Heimsch, president, DEK International GmbH, may be contacted at +41 1274 8025; e-mail: rheimsch@dek.com.