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Charting a DFT Course for Limited-access Boards
December 31, 1969 |Estimated reading time: 8 minutes
For many boards, losing access to critical nodes via an inadequate design for testability (DFT) can destroy fault coverage altogether.
By Stig Oresjo and Barry Odbert
To verify that a board works, a test engineer would prefer access to all nodes (nets) on a printed circuit board (PCB). However, for several reasons including board performance, product size, time-to-market and use of packaged components such as ball grid arrays (BGA), full electrical access has become an unreasonable expectation. At the same time, increasing evidence suggests that boards are not as defect-free as manufacturers once thought. Verifying today's boards requires designers to provide as much testability as possible and to create an effective test strategy around those designs.
Where to Begin?As a first step, one must ask, "What is full access?" Accessibility essentially falls into two categories: electrical and visual. Traditionally, electrical access means contact through a conventional bed-of-nails. On high-complexity boards, however, full access by that definition can require more nodes than an in-circuit tester (ICT) and fixture can handle effectively.
Alternately, in a distributed, intelligent test strategy, each test or inspection step looks for the failures it can find best. By contrast, downstream steps do not look for faults already identified in an earlier step. Accordingly, solder joints visible via either automated optical inspection (AOI) or automated X-ray inspection (AXI) qualify as accessible, reducing the number of electrical probe access points required for a complete test. Likewise, boundary scan can provide electrical access without a direct physical approach.
Table 1. Boards shown by product and industry, and resulting access reduction is possible while optimized for maximum fault coverage.1
Design-for-testability (DFT) decisions can further reduce the need for probe access. Test engineers examine the expected fault spectrum and aim test strategies for each fault class on the method that will find it; the test strategy ends up defining which DFT requests to focus on. Best practices, such as layout guidelines and other design rules, also simplify testing. Additionally, DFT must facilitate good diagnostic resolution to minimize diagnostic time and costs as well as to reduce scrap. In fact, excess scrap quickly overwhelms all other costs.
Generally, one approach is to test all possible solder joints with X-ray inspection and to catch everything else with ICT, an approach that requires coordinating the two methods. Available software packages assess the faults that X-ray will find and passes that information to ICT development, reducing test complexity, fixture complexity and cost. The combination also can predict the minimum number of nodes necessary to achieve good fault coverage for a particular board. Such predictions give test engineers the ammunition to get the designers' attention, especially if the information is available before layout, which makes it possible to reduce time-to-market.
Various automated test equipment (ATE) vendors provide tools to assist in selecting optimum-access points, which work best when applied during board layout. Even after layout, however, they can suggest a subset of actual board nodes for bed-of-nails access without loss of fault coverage. For many boards, losing access on a certain few, critical nodes can destroy testability. Plotting fault coverage vs. node access on a board with inadequate DFT may show coverage virtually disappearing with even a small access loss. Inability to disable the input of an oscillator, for example, can lead to unstable ICT of all downstream digital parts.
Figure 1. ICT, AXI and AOI at a glance: Considering a test strategy that uses each technology's strength can eliminate unnecessary coverage.
Leverage Boundary Scan OpportunitiesOne way to reduce the need for physical electrical access without reducing testability is to incorporate boundary scan into both devices and boards during design. Although device-level boundary scan is becoming increasingly common, board designs rarely take full advantage of the technology. Yet a boundary-scan "silicon nails" test permits the checking of conventional devices residing between boundary-scan parts without direct access to all nodes.
Companies manufacturing high-complexity boards increasingly incorporate boundary scan, often chaining 20 to 50 boundary-scan components together. One such board recently encountered contained 8,888 nodes with access to 6,000, a challenge for any electrical tester's effective capacity. Combining boundary-scan interconnect testing with silicon nails testing reduced the number of necessary nodes to about 3,450.
Even with optimal DFT, the amount of access reduction varies depending on board design. The table shows board-access reduction for PCBs by product and industry. Access points have been selected (DFT) for maximum fault coverage.
Cooperative RelationshipsDesigners know that boards need test access. Test engineers, armed with a net list and bill of materials, can perform a "quick and dirty" analysis that permits them to require that designers provide access to the most critical nodes. Adding some design rules, such as placing resistors on output-enabled lines, providing easy ways to disable clocks and inserting other control points, make the board significantly more testable.
Much DFT bias involves ICT, which remains the dominant procedure for most companies. (Its DFT requirements are better understood.) At one company*, an initial DFT review is committed to as soon as a schematic is available or when designers begin laying out the board. The test engineers must commit to a one-day turnaround, at which point, although information on test points is unknown, device access and other schematic-based issues are sought. After layout, another more formal DFT review is conducted, i.e., looking at connectivity, node locations, etc. This approach puts the test engineers into the loop of working directly with the design lab much sooner so that their relationship is more cooperative.
The most important factor in new product introductions remains time-to-market. For example, when asking for concessions such as standard pad sizes, designers generally cooperate if test engineers confer with them early enough. Asking for consistent component orientation generally meets with agreement, as will preferred parts programs, preferred and reliable supplier lists, insistence on high-quality parts, etc.
Generally, multiple sourcing also receives good response, although managers must support it. Unfortunately, multiple sourcing can complicate AOI and AXI efforts because the geometry of electrically identical parts is not necessarily consistent from one vendor to another. There is a trade-off: Designers more likely will resist testability concessions that mean adding features such as test pads and vias that require extra real estate and effort. Parts placement changes e.g., "Because of X-ray constraints, do not put this part on one side opposite that part on the other side of the board" also are not well received. Parts placement generally is the first step in board layout, and although not "cast in concrete," in most cases it is considered final.
A Changing Landscape The migration of production operations from traditional OEMs to contract manufacturers (CM) has widened the communication gap between designers and those who use their work. In particular, as actual production within OEM operations continues to fall, people with manufacturing experience move on to other jobs or other companies, resulting in a decline in both manufacturing and test expertise. Large OEMs once boasted expensive research organizations that identified and disseminated best manufacturing practices. This high-level technical knowledge base is either static or also declining.
A partnership between CMs and OEMs goes a long way toward bridging the aforementioned gap. As with the relationship between design and test engineers, it is important to recognize that both sides attempt to reduce overall costs and meet time-to-market and ramp-up goals.
Looking at the three circles in the figure and at the product's defect spectrum, a strategy that uses each technology's strength can be considered with a view toward eliminating test wherever possible. One should decide whether AOI, AXI and boundary scan make sense and use them. If company policy includes best practices in terms of board layout, CAD and design rules, they are to be incorporated into the product. When board designs come in, a test strategy should be considered that includes some combination of AOI, AXI, ICT and boundary scan, each for what it does best. Many manufacturing operations try "one-size-fits-all" strategies, for example, choosing only AOI because it is cheaper, or only caring about electrical test, in-circuit and functional, but that strategy may not be optimal. Rather, the objectives should be to minimize scrap along with sending out defect-free products. If accomplished, the time for test and repair most likely will be reduced as well.
Conclusion The ATE industry has risen to the challenge of limited board access and has provided multiple solutions. Success with a limited-access PCB is improved significantly with early communication between designer and test engineer. Their first shared task is to apply the principles of distributed, intelligent test, i.e., identifying what parts of the board do not require electrical access thanks to available automated inspection, and highlighting the optimum electrical access points. Next, the designer's use of DFT guidelines and best practices greatly eases the test engineer's challenge to reduce scrap and ensure shipment of defect-free products.
Not least are several important test techniques that maintain the advantages of ICT, including test development and component-level diagnostics automation (even in a limited-access board test environment). These techniques include boundary scan and its use to test surrounding conventional parts. Applying DFT techniques to optimize access during board layout serves to maximize test coverage.
*Agilent Technologies Inc.
REFERENCES:1. R. Balzer, "Electrical In-circuit Test Methods for Limited Access Boards," Proceedings of Etronix, February 27, 2001.2. C. Coombs, ed., Printed Circuits Handbook The Density Revolution, 5th Edition, Chapter 51, McGraw-Hill, 2001.3. T.W. Williams, K.P. Parker, "Design for Testability A Survey," Proceedings of the IEEE, Vol. 71, No. 1, Jan. 1983.
Stig Oresjo, senior test strategy consultant, and Barry Odbert, program manager, may be contacted at Agilent Technologies Inc., 815 S.W. 14th St., Loveland, CO 80537; E-mail: stig_oresjo@agilent.com; barry_odbert@agilent.com.