DARPA Rolls Out Electronics Resurgence Initiative

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With the official roll out today of the Electronics Resurgence Initiative’s latest investments, DARPA hopes to open new innovation pathways to address impending engineering and economics challenges that, if left unanswered, could challenge what has been a relentless half-century run of progress in microelectronics technology. To maintain healthy forward momentum, ERI over the next four years will commit hundreds of millions of dollars to nurture research in advanced new materials, circuit design tools, and system architectures. In addition to a half-dozen or so existing DARPA programs, and the largest program in the U.S. that funds basic electronics research at universities, DARPA is announcing today, in a trio of Broad Agency Announcements (BAAs), that ERI will add six new programs to the cause.

Image Caption: Resting on a foundation of existing research programs are newly formulated thrusts that all sum into the Electronics Research Initiative, a four-year push with anticipated annual investments in the $200 million range. Today’s BAAs fall under three major thrusts, designated here as “ERI Page 3 Investments,” which refer to research areas that Gordon Moore, one of the pioneers of the microelectronics revolution, predicted would become important for future progress. Those prognostications appear on page three of a famous paper of his, titled “Cramming More Components onto Integrated Circuits,” published originally on April 19, 1965 in Electronics magazine. Click on the image below for high-resolution.

“Moore's Law has guided the electronics industry for more than 50 years,” said Bill Chappell, director of the Agency’s Microsystems Technology Office (MTO), which will be overseeing ERI. Chappell is referring to Gordon Moore, one of the giants of the microelectronics revolution. In 1965, Moore famously predicted a trajectory of progress in which the transistor-count of integrated circuits would double every year or two while the cost per transistor would decrease. These trends have underwritten the ongoing microelectronics revolution. “Moore’s Law has set the technology community on a quest for continued scaling and those who have mastered the technology to date have enjoyed the greatest commercial benefits and the greatest gains in defense capabilities,” said Chappell.

Moore’s Law still applies, but the design work and fabrication now required to keep on pace is becoming ever more difficult and expensive. “The current trajectory is straining commercial and defense developments,” said Chappell.

This is where ERI comes in. The foundation for the Initiative has been building for a number of years in the form of existing MTO programs such as DAHI, CHIPS and CRAFT, which address ERI’s three research pillars: materials and integration, circuit design, and systems architecture. Another major ERI component is the extensive university-based program—the Joint University Microelectronics Program (JUMP)—that MTO and corporate partners have organized to build up a fundamental research base in fields underlying microelectronic technologies. The six programs described in the three BAAs posted today represent new annual investments of $75 million in ERI’s three pillars, which map onto research areas that Gordon Moore predicted would eventually become the required base for advances when scaling no longer leads to lower cost.

The ERI Materials and Integration thrust, outlined in the BAA designated as HR001117S00056, features two programs that emerge from this question: Can we use integration of unconventional electronics materials to enhance conventional silicon circuits and continue the progress in performance traditionally associated with scaling? The Three Dimensional Monolithic System-on-a-Chip (3DSoC) program focuses on developing materials, design tools, and fabrication techniques for building microsystems on a single substrate with a third upward dimension, compared to the usual flat, two-dimensional format for microelectronic chips. A primary payoff of this program could be more efficient packing of logic, memory, and input/output (I/O) elements in ways that dramatically shorten—more than 50-fold—computation times while using less power. The second and related program within this BAA is the Foundations Required for Novel Compute (FRANC) program. Its goal is to transcend the conventional separation of logic and memory functions in what are known as von Neumann architectures (named after the pioneering mathematician, physicist, and computer scientist John von Neumann). The time delay and energy expended in moving data between memory components that store it and processors that act on it are the primary constraints on computer performance today. Those submitting research proposals for this program will need to show how they might overcome this “memory bottleneck” by developing novel materials, components, and algorithms to speed the movement of memory in and out of logic circuitry or by devising entirely novel structures in which logic and memory circuitry are more intricately meshed than ever before.

The ERI Design thrust, outlined in the BAA designated as HR001117S0054, is driven by this question: Can we dramatically lower the time and complexity required to design modern SoCs, and unleash a new era of circuit and system specialization? The thrust is comprised of two new programs—The Intelligent Design of Electronic Assets (IDEA) program and the Posh Open Source Hardware (POSH) program. An endpoint of the IDEA program would be the capability for a “no human in the loop,” 24-hour design framework that would enable even nonexperts to design complex electronic technologies, including mixed-signal integrated circuits, system-in-package modules with multiple integrated circuits (ICs), and printed circuit boards. The complementary POSH program would deliver an open-source design and verification framework, including technologies, methods, and standards, which would enable cost-effective design of ultra-complex SoCs. DARPA’s ERI team expects that new tools that lower the barrier to complex SoC design will enable a new era of innovation in application-specific designs, much in the way that open source software has enabled innovation at the application level.

The ERI Architectures thrust, outlined in the BAA designated HR001117S0055, is based on the following question: Can we enjoy the benefits of specialization in the chip but still rely on general programming constructs? Like the other two thrusts, this third one seeks proposals for two new programs. The Software Defined Hardware (SDH) program has its sights ultimately on a decision-assistance technology base for designing and manufacturing reconfigurable hardware and software that can run data-intensive algorithms (which are likely to underlie future machine learning and autonomous systems) with the performance of today’s specialty circuits known as Application Specific Integrated Circuits (ASICs). In modern warfare, decisions are driven by information coming from, for example, thousands of sensors providing ISR (intelligence, surveillance, and reconnaissance) data, logistics/supply-chain data, and personnel performance measurements. “Utilization of this data relies on computational algorithms running at huge scale,” according to the BAA. The Domain-Specific System on a Chip (DDSoC) program of the Architectures thrust is driven by the need to rapidly develop multi-application systems through a single programmable framework. Such a framework would enable SoC designers to mix and match general purpose, special purpose (e.g., ASICs), and hardware accelerator coprocessors, as well as memory and I/O elements, into easily programmed SoCs for applications within specific technology domains. One such domain is software-defined radio, which encompasses mobile communications, satellite communications, personal area networks, all types of radar, and applications in the electronic warfare space.

“These new ERI investments, in combination with the investments in our current programs and JUMP, constitute the next steps in creating a lasting foundation for innovating and delivering electronics capabilities that will contribute crucially to national security in the 2025 to 2030 time frame,” said Chappell.

The next concrete step in moving forward on ERI’s six new programs is for interested researchers to gather at Proposers Days for each thrust. The Proposers Day for the Architectures thrust’s two programs, DSSoC and SDH, will take place just a few blocks from DARPA headquarters in Arlington, VA, on Sept. 18 and 19, respectively. The Proposers Days for both programs in the Design thrust—IDEA and POSH—will take place on Sept. 22, in Mountain View, Calif. The FRANC program of the Materials and Integration thrust will be run in the form of a webinar on Sept.15 and that thrust’s other program, 3DsoC, will take place at DARPA headquarters in Arlington, VA, on Sept. 22. For details about all of these Proposers Day events and how to register, consult the Special Notice, DARPA-SN-17-75, which is posted on fbo.gov.