Reliability of ENEPIG by Sequential Thermal Cycling and Aging

Estimated reading time: 6 minutes

The IPC standards team has helped in easing the implementation of ENEPIG surface finish for PCBs by releasing a standard with a large characterization database. This data and that generated by industry generally concentrated only on the basic testing approaches and mostly for lead-free solders and testing of individual solder ball attachments rather than the advanced ball grid arrays (BGAs) electronic packaging assemblies and for tin-lead solder. It is extremely difficult to correlate test results from the shear of individual balls to the assemblies of BGAs. Reliability testing using BGA packages, especially land grid arrays, with tin-lead solder is lacking. In addition, controversy exists regarding the reliability/compatibility of ENEPIG with tin-lead solder, as there are more consistent positive test results for the lead-free solder joints. A hot air solder level (HASL) finish, which is commonly used for the tin-lead solder, lacks the flatness requirement for the fine pitch ball grid arrays (FBGAs).

The significance of the PCB surface finish on assembly reliability was recognized by the IPC 9701 standard team in its early development, when the team was narrowing the requirements for the tin-lead solder joint testing for the BGA packaging technologies. The team limited the use of the PCB finishes to solder preservative (OSP) and HASL to minimize the potential for premature failures by using other finishes. Such restriction was implemented to avoid significant cost and schedule burden on smaller facilities, which generally lack knowledge and experience on the nuances of unique surface finishes such as electroless nickel/immersion gold (ENIG). This specification allowed unique surface finishes only for comparison to the baseline finish. The A revision, which also includes recommendations for Pb-free solders, allowed only the use of an OSP finish since the tin-lead HASL was not compatible to Pb-free solders. Other surface finishes including silver (Ag) and tin (Sn) were acceptable only for a manufacturer’s internal data comparison. Also, an ENIG finish could be used for an internal data comparison; however, it was warned that the risk of introducing unintended brittle failure (black pad) could occur. The ENEPIG was not introduced at this time; therefore, this specification does not discuss this specific surface finish.

With the industry implementation of Restriction of Hazardous Substances (RoHS), the use of a tin-lead HASL finish for PCB with excellent solderability and solder joint reliability has diminished even though this still is the dominant finish for high-reliability applications with tin-lead solder. The process consists of immersing PCBs in a tin-lead alloy followed by solder removal using air knives, which blow hot air across the surface of the PCB [to remove excess solder]. The lead-free HASL finish has gained some interest for RoHS use, but it suffers from increased copper dissolution and lacks the flatness requirement needed for finer pitch array packages. An ENIG finish provides the flatness requirements with excellent solderability, but it suffers from the “black pad” potential failure and lacks gold wire bondability that is required for hybrid (wire and solder) technologies.

ENEPIG has provided the best solution for the black pad defect by depositing an additional layer of electroless palladium over nickel. The palladium is not etched away during the gold plating process so the potential for the oxidation of nickel (black pad) is eliminated. However, ENEPIG is costlier than ENIG. ENEPIG also provides excellent solder joint reliability for leadfree solder joints, but industry debates continue on its reliability with tin-lead solder assembly.

The IPC-4556 specification for ENEPIG is very comprehensive and includes a wealth of information. The thickness specification for ENEPIG specified as: 1) Nickel: 3 to 6 μm (118.1 to 236.2 μin), 2) Palladium: 0.05 to 0.15 μm (2 to 12 μin), and 3) Gold: a minimum thickness of 0.030 μm (1.2 μin). All measurements are to be taken on a nominal pad size of 1.5 mm x 1.5 mm (0.060 in x 0.060 in) or equivalent area. The new amendment sets an upper limit for the gold thickness at 2.8 μin (0.7 μm) to discourage requests for a much higher immersion gold value and avoid its negative effect on reliability. A higher gold thickness will increase dwell time in the gold bath resulting in nickel corrosion under the palladium layer.

This investigation addresses the reliability from an assembly perspective and more realistic thermal cycles and aging environmental conditions. ENEPIG is yet to be widely accepted for high-reliability applications with tin-lead solder assembly. First, technology trends for LGA are discussed followed by an example of the difficulty of reflow for HASL with PCB surface finish compared to ENEPIG finish. Then, briefly discussed is assembly on a PCB with ENEPIG finish using two advanced area array packages, one an LGA with 1156 solder joints and the other one with CLGA 1272 (ceramic LGA) LGAs. The LGAs were subjected to 200 thermal cycles (-55°C to 125°C). Optical and SEM photomicrographs showing solder interface conditions after 200 thermal cycles (TC) are presented and were compared to samples that were subject to additional 324 hours of aging at 125°C. Furthermore, these were compared to those that were subjected to an additional 100 thermal shock cycles (-65°C to 150°C). The article concludes with a summary and recommendations for the next steps of investigation.

LGA and Advanced Packaging Trends

This article focuses on the second-level (board-level) solder joint reliability and intermetallic formation of LGA1156. Figure 1 categorizes single-chip microelectronics packaging technologies into three key technologies:

• Plastic ball grid arrays (PBGAs) including flip-chip die version (FCBGA), land grid array (LGA) with solder balls, quad flat no lead (QFN) and new versions

• Ceramic ball grid array (CBGA), ceramic column grid arrays (CGAs), and ceramic LGA version9

• Chip-scale packages, smaller footprint versions of BGA, and wafer level packages (WLPs)

Figure 1: Single chip packaging technologies covers three main categories. LGA exists in all three categories.

PBGAs and CSPs are now widely used for many commercial electronics applications, including portable and telecommunication products. BGAs with 0.8−1.27 mm pitches are implemented for high-reliability applications and generally demand more stringent thermal and mechanical cycling requirements. The plastic BGAs introduced in the late 1980s and implemented with great caution in the early 1990s, further evolved in the mid-1990s to the CSP (also known as a fine-pitch BGA) having a much finer pitch from 0.4 mm down to 0.3 mm. Recently, fan-out and fan-in wafer level packages have gained significant interest. LGA packages cover a range of counterpart packages from fine pitch CSP to large pitch and high I/O BGAs. Similar to ball array versions, LGAs are surface-mountable.

There are no solder balls in LGAs, only land pattern terminations like QFNs. Interconnections are formed using solder paste and reflow during surface mount assembly—reducing the assembly height. This allows for a thinner assembly needed for mobile and computing products, especially the RF application that requires lower parasitic noise. LGAs are the preferred packages for applications that require an ideal combination of low device sizes and profiles, and superior thermal and electrical performance. LGAs have negligible internal stray parasitic elements associated with their external solder pads and closeness to PCBs which enable an extremely low thermal resistance to the device. This enables maximum heat transfer from the die to the package pads. However, thermal cycle reliability has an inverse exponential relationship with solder joint height. Therefore, there is a possible significant reduction in solder joint reliability. FEA modeling projects lower cycles-to-failure trends for LGAs compare to BGAs, which are also verified by testing.

To read the full version of this article, which appeared in the October 2017 issue of SMT Magazine, click here.