35 Years of HDI Fabrication Processes and Obstacles for Implementation

Estimated reading time: 2 minutes

Introduction

The electronics industry is the world’s largest and most robust market. It is also a bulwark of American creativity, with Silicon Valley as its origin and fortress. The SIA Roadmap is still pushing the size of wafer transistors smaller and smaller, with the resulting faster rise times and need for finer pitch. But silicon needs a mounting platform and the printed circuit and organic IC package will be needed to create working products.

For North America, there is a growing need for more HDI capability. Some of the reasons for the slower adoption of HDI fabrication in N.A. may rest with four obstacles: Defining density needs; EDA tools not providing increased functionality; process controls for fabricating reliable microvias; and bare-board/ICT solutions once HDI is assembled.

A wakeup call may be too strong a term, but it is time to seriously consider what you are going to do about HDI. The adage “offshore can’t handle our technology” is out of date. Offshore (or Asia) can now do 24-layer multilayers, laser-drilled HDIs, fine lines (2-mil traces and spaces), flip chip packages, pure gold, hard gold, low loss materials, RF, buried capacitance, mixed dielectrics, etc. The current production analysis of HDI technology released by TechSearch International in “HighDensity Microvia Substrates: Markets, Applications and Infrastructure−Updated” shows that Asia had 86% of the HDI business in 2016−2017.

As you can see in Figure 1, North America is a mere 5% of the total. TechSearch predicts that HDI will grow to $18.6 billion by 2020. Now you might ask, why is this so? The two main uses for HDI are for portable products like cellular phones and camcorders and for finepitch IC packages. It just happens that Japan, Korea and Taiwan make a lot of these products and we don’t. In fact, at the Electronics Circuits World Conference 14, companies like Samsung have been working on new lower-cost laser HDI technologies using thermoset resins. This eliminates the need for lamination presses and lowers the material costs in the production of microvias.

Lately, my time has been monopolized by OEMs asking about the most cost-effective way to use the new 0.5 mm BGAs. Many of these are digital signal processors (DSP) and custom ASICs in the 457 to 1384 I/Os range. These are being produced in the millions now and are going into all sorts of sophisticated servers, networking and telecom products. These industrial products will now form the third platform for HDI. These products also make up a majority of the high value-added electronics produced in North America.

The reason for the increase in fine-pitch BGA activity can be seen in Figure 2. In 2016, BGAs are approaching the costs of quad flat packages and complex (high pin count) packages now cost less than one cent per pin. With package prices like that, all OEMs are considering how to use them in their new products.

To read the full version of this article which appeared in the November 2017 issue of The PCB Magazine, click here.