AltiumLive Munich: Day 2 Keynotes

Estimated reading time: 12 minutes

Automotive companies had their own design rules, and designs were negotiated very hard and tested intensively. Car power systems were never “clean,” and EMC limits were very low. His advice was to seek experienced help before embarking on one’s first automotive design, to recognise the importance of every requirement written into the specification—even if it was not obvious at the beginning of the project—and to do intensive research on OEM design rules. Automotive components were sometimes hard to source and were generally more expensive than industrial grade; although not necessarily better, and long-term availability was essential. “The automotive industry is the mother of process-oriented development. Be prepared for the overhead caused by project management and documentation.”

Anticipating design issues associated with the ongoing development of electric vehicles, his list included noisier power systems, significant voltage, current peaks, and strong magnetic fields. Many new issues would come to light as OEMs learned how to make electric vehicles and customers learned how to use them.

Towards the end of his AltiumLive 2017 presentation, Wischnack had been joined by freelance design expert Rainer Beerhalter for a real-time review of one of his projects, and that initiative had been so popular that we were treated to a repeat performance. The object of critical analysis this time was a six-layer PCB that Beerhalter had designed as part of a modular control system for large LED displays. Again, it proved to form the basis of a lively interactive audience participation session that inevitably ran well over time, although no one seemed overly concerned at missing their coffee break!

Max Seeley on Schematics

The second keynote of the second day was craftily timetabled as the final afternoon session—possibly a way to encourage the audience not to think about creeping away early? It was well worth the wait. Max Seeley, lead electrical engineer for the digital solutions group at 3M’s corporate research laboratories, reviewed some of his early life experiences, particularly ones that had scared him. “What makes me an engineer? It’s not what I know, but how I approach problems.” His definition of success was the ability to work through adversity. And he advocated a systematic and structured approach to a design project. “PCB layout starts in the schematics.”

Seeley reviewed his design objectives such as reducing design cycles, dealing with issues proactively instead of reactively, producing a high-quality PCB layout that would pass regulatory compliance testing, and saving his company time and money. And what were the essential purposes of schematics? They communicated design intent and were effectively blueprints for the entire design including the layout; they promoted design reuse and contributed to robust design analysis and reviews.

He showed a typical “old-school” schematic, which in his view, was confusing, gave little idea as to how the circuit functioned, was extremely difficult to review, and didn’t do much more than help him join the dots. But in many ways the old-school, mentality persists to the present day. What could be done to change it? Was there a better way?

Seeley proposed that a good schematic should start with a title page to give an overview and help people find what they were looking for. This page would include critical information like the project name, variant, date the schematics were created, and date the schematics were released together with the relevant PCB part numbers. He further stressed the importance of also including brief design and layout notes to draw immediate attention to critical features. Good design notes could help avoid costly respins. He suggested that the goals of a top-level schematic should be to show the overall connectivity of the design and the way the design was organised to give insight into functional blocks and how they interfaced to the rest of the design.

A power tree included in the schematic saved a lot of tedious work trying to derive it later in the process, and allowed the dependencies to be seen; similarly, a list of the output voltages and maximum currents of the voltage regulators would be helpful. Another schematic Seeley would include would be the power consumption of the system per power net to enable the maximum power capability and current consumption on a particular rail to be calculated. That information was directly relevant to the pulse-density modulation analysis, and to have it readily accessible saved searching data sheets for individual values. It also helped with doing meaningful simulation.

Likewise, power delivery network analysis was made easier if minimum and maximum input voltages for critical devices were listed. A table showing power sequencing was also extremely useful, and Seeley believed you should include 3D representations post-layout to give a visual reminder of how the board was structured and the positions of key components. He also recommended including copies of suppliers’ I/O multiplexer tables in the schematic.

Seeley always spent time working with the PCB fabricator to optimise the board stackup, and then included it in the schematic as a reference to check against at the end of the design process before sending the design for manufacture. And a useful additional feature of Altium Designer 19 was the ability to generate an impedance table in the output documentation.

Returning to his top-level schematic with a reminder that the goals should be to show the overall connectivity of the design and the way the design was organised, and to give insight into functional blocks and how they interfaced to the rest of the design, he discussed specific functional blocks, power nets, and net names. He had colour-coded the schematic per function and for ease of review. Also, he recommended that the parameters of individual components be clearly shown in the schematic, and that every power rail should be labelled with its actual value rather than just its generic.

Seeley considered connectors to be the weak point of any design and recommended that a dedicated schematic be prepared for each example with particular attention to the adequacy of filtering and ESD protection. He also advocated a table of descriptive net classes, commenting that net classes were what should be driving the PCB layout rules and be an indication of how the rules were created. He went into some depth of discussion of his techniques and processes for pre-layout simulation and checking that he was working within his crosstalk thresholds.

Seeley repeated his objectives that the schematic should communicate design intent, be a blueprint for the entire design including the layout, promote design reuse, and contribute to robust design analysis and reviews. He was not concerned that his schematics were becoming too busy provided that they were readable and reviewable. Along the way, he made several useful suggestions as to additional functions that Altium could include in their later revisions.

Seeley’s account of his principles and practices succeeded in captivating his audience and holding its attention until late in the afternoon. And an extra bonus awaited those who didn’t sneak off when he had finished—the raffle! Attendees had been issued with raffle tickets when they registered, and when they attended the breakout sessions, so there were spectacular prizes to be won including drones and a 3D printer.

Feeling Inspired

Judy Warner wrapped up the proceedings, thanking the sponsors and all those who had attended and presented with particular acknowledgement to Lawrence Romine, Sara Hosley, and the Altium team for their outstanding efforts in organising and managing an enormously successful event that succeeded overwhelmingly in realising its “learn, connect, and get inspired” objective.

Visit I-007eBooks to download your copy of Altium micro eBook today:
The Printed Circuit Designer's Guide to...Design for Manufacturing (DFM)

• < Previous Page