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Current IssueThe Hole Truth: Via Integrity in an HDI World
From the drilled hole to registration across multiple sequential lamination cycles, to the quality of your copper plating, via reliability in an HDI world is becoming an ever-greater challenge. This month we look at “The Hole Truth,” from creating the “perfect” via to how you can assure via quality and reliability, the first time, every time.
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EM Modeling: The Impact of Copper Ground Pour on Loss and Impedance
May 2, 2019 | Chang Fei Yee, Keysight TechnologiesEstimated reading time: 1 minute

This article briefly introduces the general purposes of copper ground pour on printed circuit boards. Subsequently, the impact of copper ground pour on PCB channel loss in terms of insertion loss and impedance in terms of time domain reflectometry (TDR) is studied with electromagnetic modeling using Mentor HyperLynx.
Introduction
Copper ground pours are created by filling open, unpopulated, or unrouted areas on outer layers of the PCB with copper. Subsequently, copper fill is hooked up to ground planes on inner layers with stitching vias as depicted in Figure 1. Copper ground pours on outer layers provide extra shielding against electromagnetic radiation by signals on inner layers. Besides that, copper pour also serves as a heat sink for the voltage regulator module on PCBs. In terms of manufacturability, copper pour reduces the possibility of PCB warpage during reflow by balancing the amount of copper on each side of the PCB.
However, copper ground pour comes with some disadvantages, as there is a change in impedance of PCB trace adjacent to ground pour (i.e., impedance decreases when copper pour becomes closer to the PCB trace). As a result, the impedance mismatch contributes additional PCB loss to the transmission line at a high-frequency range.
Analysis and Results
To study the impact of copper pour on PCB channel loss in terms of insertion loss and impedance in terms of TDR, five models of 1” single-ended microstrip listed in Table 1 were created. The simulation topology is shown in Figure 2. For model 1A, a microstrip trace 5 mils wide and 1 oz. thick is laid out 2.65 mils above the reference plane insulated by low-loss dielectric substrate material. This trace is sandwiched between two ground traces on the same outer layer. The spacing between each adjacent ground trace and the signal trace is 1x the signal trace width. Meanwhile, the spacing between each ground and signal trace is set as 2x, 4x, 6x, and 8x for model 1B, 1C, 1D and 1E, respectively.
To read this entire article, which appeared in the April 2019 issue of Design007 Magazine, click here.
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