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Advancement of SPI Tools to Support Industry 4.0 and Package Scaling
August 6, 2019 | A. Prasad, L. Pymento, S.R. Aravamudhan, and C. Periasamy, Intel Corp.Estimated reading time: 13 minutes
Another point to be noted is that the majority of these tools (except A+ and B) employ Z-height threshold >10 um to estimate. They ignore the height and volume of the metal pad in the solder paste deposit calculation. For large volume deposits, metal pad volume contribution will be small and may not affect accuracy bias as much. Software algorithms and implementations can vastly vary from vendor to vendor. It is clearly evident that threshold-free measurements, along with correct hardware, is more accurate for low-volume solder paste deposits.
Figures 7a and b: Variability chart for bias % for Phase 3 volume range.
Conclusions and Recommendations
The results of the study showed increased sensitivities to low solder deposits of less than 250 cubic mils across SPI equipment employing threshold algorithm values >10 µm and spatial resolution ≥7 µm. Evaluations on a 5-µm resolution system (A+ tool) employing 0-µm threshold algorithms were found to have acceptable accuracy deviations of less than ±20%.
To improve inline SPI accuracy for low solder paste volume deposits, SPI vendors must consider calibration of SPI tools with lower-volume (below 200 cubic mils) NIST or equivalent standards. For fine-pitch applications, as well as lines configured for Industry 4.0, accuracy should be a consideration for SPI tool selection.
Acknowledgments
The authors would like to acknowledge the Intel internal team and the engineering teams at various SPI vendors for their help in completing the SPI measurements and answering inquiries about the tool capabilities.
References
- C. Shea, and R. Farrell, “Stencil and Solder Paste Inspection Evaluation or Miniaturized SMT Components,” Proceedings of SMTA International, 2013.
- J. M. Peallat, “New Opportunities for 3D-SPI,” www.circuitnet.com, 2008.
- CyberOptics, “‘True’ Heights Measurement in Solder Paste Inspection (SPI),” www.cyberoptics.com, 2013.
- H. Biemans, “5D Solder Paste Inspection: Merits Beyond 3D Technology,” Global SMT & Packaging, 2011.
- C. Periasamy, and S. Walwadkar, “A Scanning Chromatic Confocal Microscope for Accurate Off-Line Solder Paste Volume Measurement,” Proceedings of SMTA International, 2017.
- Intel internal survey report.
This paper was originally presented at the Technical Proceedings of SMTA International 2018.
Authors
Abhishek Prasad is a process engineer at Intel Corporation.
Larry Pymento is a senior process/technology development program manager at Intel Corporation.
Srinivasa R. Aravamudhan is a process technology development engineer at Intel Corporation.
Chandru Periasamy is a packaging R&D engineer, metrology and mechanics, at Intel Corporation.
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