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Trouble in Your Tank: A Process Engineer’s Guide to Interconnect Defects
For those associated with PCB fabrication, one of the biggest nightmares is the infamous interconnect defect (ICD). Essentially, an ICD is a separation of the plating from the interconnect foil. The industry typically classifies this defect into four categories. Type 1 describes the situation where the electroless copper separates from the inner layer copper face. Of course, there are other types of separation that can be encountered.
It is well known that the electrolytic copper may separate from the electroless copper, but the electroless copper remains on the interconnect. This situation is referred to as Type 2 ICD. Whereas Type 1 references the electroless copper separating from the inner connect post or inner plane, there is a third type where the electroless copper deposit separates from itself. This is more like a cohesive failure within the deposit. Type 3 is very difficult to detect and requires excellent micro-sectioning and polishing techniques to properly detect and troubleshoot the root cause. Finally, one defect you may encounter is the fourth type of ICD, D-Sep.
Type 1
A type 1 ICD occurs due to a number of factors. First and foremost, an extremely high rate of deposition introduces internal stress into the electroless deposit. When the deposit is highly stressed, most thermal excursions will cause the copper deposit to separate from the inner layer post. The separation can be as little as a hairline fracture to small separations along the face of the post. One solution to mitigating a Type 1 ICD is to slow down the rate of copper deposition. Also, it prevents over-catalyzation (excessive palladium at the interconnect face) and reduces operating temperatures.
D-Sep
D-sep is also a separation of the electroless copper deposit from the interconnect. However, unlike a Type 1 ICD, which occurs after a thermal excursion (solder shock, assembly, etc.), D-sep occurs without any thermal stress (Figure 1).
Figure 1: D-Sep.
D-sep is caused by excessive stress in the deposit, allowing the separation that resembles the letter “D,” hence the name. Other possible root causes relate to the interruption of the plating mechanism that leads to a misoriented grain structure of the copper deposit, whereas with a Type 1 ICD, a thermal excursion is required to cause the separation of the electroless copper from the post (Figure 2).
Figure 2: Type 1 ICD.
One can easily surmise that a Type 1 ICD and D-sep are the result of a highly stressed copper deposit. However, there are several other potential causes of these issues that must be considered. Deposit stress can be introduced in a variety of ways.
Since D-sep occurs without the application of a thermal excursion, a skilled troubleshooter would look at the following areas. This exercise includes both chemical and mechanical parameters related to the electroless copper process. The main cause of D-sep can be summarized as a change in the deposition conditions of the copper deposit. This is not due to drill smear remaining on the interconnect post. The change in key chemical parameters, including the hydroxide concentration, solution specific gravity, and solution temperature are outlined as follows:
- Low caustic level: Depleting the caustic stops the plating reaction.
- High specific gravity: By-product components are produced that have an inhibiting effect on the chemical plating, most notably sodium sulfate and sodium formate.
- Vibration: Vibration removes air bubbles that may be trapped in the hole as it enters the tank. Hydrogen gas is produced during the reaction and needs to be removed from the holes.
- The temperature of electroless: Higher temperature increases the plating rate. If solution is not transferred fast enough, the reaction stops.
As the following reaction shows, the electroless copper plating solution ages over time with the buildup of formate, carbonate, and chloride as by-products. These by-products are measured with specific gravity but are not individually differentiated. Chloride increases linearly with the consumption of cupric chloride. Carbonate is formed as carbon dioxide from the air reacts with sodium hydroxide in the bath. Assuming air flow is constant, carbonate will build linearly. Formate also tends to grow linearly at low levels through several reactions:
Formate and other by-products contribute to the increase in specific gravity, which reduces plating rates. With this situation, one can find the occurrence of D-sep.
Some ways to prevent D-sep include:
- If D-sep occurs, raise the caustic level in the electroless copper solution to 9.5 g/L
- Lower the operating temperature of the copper plating solution
- Reduce the specific gravity of the bath
- Increase the ability of the solution to flow through the holes
- Increase vibration
- Increase solution movement
- Ensure proper rack agitation
- Open up the spacing between boards
Other areas that will help include:
- Increase rinsing to clean the holes
- Raise the temperature of the rinse water
- Increase the pH of the rinse before electroless
- Ensure desmear is giving a clean hole and not dragging any chemistry down the line
Conclusion
As a process engineer, one must be able to discern the difference between a Type 1 ICD and D-sep for the simple reason that the root causes are different. Thus, the troubleshooting exercise will require one looks at different areas of the fabrication process to properly solve the ICD.
This column originally appeared in the September 2020 issue of PCB007 Magazine.
More Columns from Trouble in Your Tank
Trouble in Your Tank: Interconnect Defect—The Three Degrees of SeparationTrouble in Your Tank: Things You Can Do for Better Wet Process Control
Trouble in Your Tank: Processes to Support IC Substrates and Advanced Packaging, Part 5
Trouble in Your Tank: Materials for PWB Fabrication—Drillability and Metallization
Trouble in Your Tank: Supporting IC Substrates and Advanced Packaging, Part 5
Trouble in Your Tank: Electrodeposition of Copper, Part 6
Trouble in Your Tank: Electrolytic Copper Plating, Part 5
Trouble in Your Tank: Processes to Support IC Substrates and Advanced Packaging, Part 4