Cadence Integrity 3D-IC Platform Supports Advanced Multi-Chiplet Designs

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Cadence Design Systems, Inc. announced that it is working with TSMC to accelerate 3D-IC multi-chiplet design innovation. As part of the collaboration, the Cadence® Integrity™ 3D-IC platform, the industry’s first unified platform for 3D-IC planning, implementation and system analysis, is enabled for TSMC 3DFabric™ technologies, TSMC’s comprehensive family of 3D silicon stacking and advanced packaging technologies. In addition, the Cadence Tempus™ Timing Signoff Solution has been enhanced to support a new stacking static timing analysis (STA) signoff methodology, shortening design turnaround time. Through these latest milestones, customers can confidently adopt the Cadence 3D-IC solution and TSMC’s 3DFabric technologies to create competitive hyperscale computing, mobile and automotive applications.

The Cadence 3D-IC solution supports TSMC’s full set of 3D silicon stacking and advanced packaging technologies, including Integrated Fan-Out (InFO), Chip-on-Wafer-on-Substrate (CoWoS®) and System-on-Integrated-Chips (TSMC-SoIC™). The 3D-IC solution also aligns with the Cadence Intelligent System Design™ strategy, driving system-on-chip (SoC) design excellence.

The Cadence Integrity 3D-IC platform provides 3D chip and package planning, implementation and system analysis in a single, unified cockpit. This lets customers streamline multi-chiplet design planning, implementation and analysis of 3D silicon stacking while also optimizing engineering productivity, power, performance and area (PPA). Also, the platform has co-design capabilities integrated with the Cadence Allegro® packaging technologies and the Cadence Virtuoso® platform, enabling complete 3D integration and packaging support.

To benefit customers further, Cadence analysis tools are tightly integrated with the Integrity 3D-IC platform and work seamlessly with TSMC 3DFabric technologies, enabling system-driven PPA. For example, the Tempus Timing Signoff Solution, which incorporates rapid automated inter-die (RAID) analysis, a part of Cadence’s 3D STA technology, helps customers create multi-tier designs with accurate timing signoff. The Cadence Celsius™ Thermal Solver is enabled to support hierarchical thermal analysis for multi-die stacking, SoCs, and complicated 3D-ICs. In hierarchical analysis, hotspots are modeled with finer grids, which enable customers to achieve runtime and accuracy targets. The Cadence Voltus™ IC Power Integrity Solution offers customers thermal, IR drop and cross-die resistance analysis for design robustness. For more information on the Cadence 3D-IC solution, visit www.cadence.com/go/3DICsolpr.

“This joint effort between TSMC and Cadence confirmed that the Integrity 3D-IC platform and signoff and system analysis tools support TSMC’s advanced 3DFabric chip integration solutions, providing our mutual customers with flexibility and ease of use,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “The result of our long-term collaboration with Cadence enables designers to take full advantage of the significant power, performance and area improvements of TSMC’s advanced process and 3DFabric technologies, while accelerating innovation for their differentiated products.”

“By working to ensure our Integrity 3D-IC platform supports TSMC 3DFabric technologies, we’re advancing our longstanding collaboration with TSMC and facilitating design innovation in several emerging areas, including 5G, AI, and IoT,” said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “TSMC’s 3DFabric offerings paired with Cadence’s integrated, high-capacity Integrity 3D-IC platform, Tempus Timing Signoff Solution, Allegro packaging technologies and 3D analysis tools provide our mutual customers with an efficient solution to deploy 3D design and analysis flows for the creation of robust silicon-stacked designs.”