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Estimated reading time: 6 minutes
All Systems Go! Ensuring Power Integrity—Explore, Design, and Verify
When designing an electronic system, ensuring power integrity (PI) is all about making sure that the power you are putting into the system via the voltage regulator module (VRM) reaches the downstream components in an efficient, sufficient, and stable manner.
In the not-so-distant past, ensuring the PI of an electronic system was a relatively simple and pain-free task. Many products involved a single PCB populated by readily available off-the-shelf ICs, such as the classic 7400-series devices from Texas Instruments. For the purposes of PI, these ICs, which were presented in low pin count, coarse pin pitch packages could be treated as closed boxes represented by simple power models.
Meanwhile, in the case of traditional multi-board systems, the boards were typically plugged into—and powered by—a common backplane. This meant that, from a PI perspective, so long as each board met its total power budget, the boards could be largely designed and verified in isolation.
Time marches on and so things have indeed changed. Many of today’s electronic designs feature multiple PCBs connected directly together, where each board may be populated by a mix of discrete components, off-the-shelf ICs and custom system-on-chip (SoC) devices. These high-capacity, high-performance, high pin count, fine pin pitch ICs and SoCs have sophisticated PI models associated with them. Many boards also feature system-in-package (SiP) devices in which multiple chiplets (unpackaged silicon die) are mounted on a common interposer and presented in a single package. Such interposers may be formed from a variety of materials, with silicon providing the finest features and highest interconnect densities. Each SiP may be considered as a small, specialized board in its own right. In the case of this class of design, at some stage PI will have to be performed on the entire system, including all the ICs, SoCs, SiPs, PCBs, connectors and cables.
From the simple to the complex and irrespective of any specific design methodology, the electronic product development flow can largely be segmented into three main phases (Figure 1). The exploration phase occurs pre-design where you are making feasibility decisions and evaluating tradeoffs. This is followed by the design phase in which you capture the logic (functionality) and create the layout for all the SiPs and PCBs. And then there’s the post-layout verification stage where you (or your verification team) perform detailed verification to decide if you can sign off the design before you commit to spending a lot of money in fabrication and manufacturing.
Figure 1: The PI process.
Historically, PI signoff verification tools have—not surprisingly—focused on the post-layout verification signoff portion of the workflow. This is where you have access to the detailed physical layout, which allows you to perform detailed extraction. Using these extraction results, you can perform AC analysis to look at things like decoupling capacitors, power ripple, and frequency domain impedance. Similarly, the extraction results can be used to perform DC analysis to determine IR drops throughout the design. In the case of today’s designs, this analysis needs to be performed on the power distribution network (PDN) at the package, board and full system levels.
More recently however, the industry has embraced a shift-left philosophy in which the quality of the design will be improved—and any risks associated with the design will be minimized—by starting verification tasks as early as possible in the design process. A key feature with respect to a meaningful realization of this philosophy is to extend the signoff verification tools with capabilities that are more suited to designers and to make these capabilities accessible from within the designers’ existing tools.
As illustrated in Figure 1, this means shifting-left system-level PI all the way into the exploration phase. Today’s state-of-the-art development environments provide a host of new capabilities. For example, they allow you to start with a blank canvas in the exploration phase, putting down high-level models and pre-layout power topologies, running very early simulations all the way from the VRM to the consumers (loads) and making tradeoffs along the lines of, “What if I put my decoupling capacitors in the package? What if I put them on the board? And what’s the power ripple going to look like if I have two banks of memory rather than one?” The ability to make early decisions as to where everything will go allows you to do a better job (engineer a better solution) once you proceed to the more detailed implementation.
When you do get to the design portion of the workflow, you can start to flesh out your original high-level models and topologies with more details. All the extraction engines create models that are gathered into a full-system PDN simulation canvas. This canvas may be thought of as a graphical SPICE representation of a hierarchy of blocks with associated sub-circuits and attributes like S-parameters, RC models, piecewise linear (PWL) current models and so forth.
The same extraction engines used in signoff verification can be used throughout the flow to feed full system PDN simulations. The only difference is in the amount of detail available to the engines—and therefore the resolution of the simulations—at each stage in the workflow (Figure 2).
Figure 2: Data flow for full-system PI analysis.
The ability to take the high-level representation of the PDN you created during the exploration portion of the flow and use it as a starting point in the design portion of the flow saves time and effort. Performing PI analysis at the schematic level allows you to evaluate your decoupling strategies and IR drops in order to get the right components into the schematic. Similarly, having the ability to perform in-design PI analysis, providing feedback directly in the layout tools, allows you to push and shove components, tracks and vias around and immediately see the results.
This new type of system-level PI flow allows you to run full system simulations to obtain frequency domain results, power ripple time domain results, and IR drop results from the VRM to the current consumers wherever you are in the design process. Furthermore, it allows you to sweep things like models, S-parameters, SPICE parameters, on-die parasitics and current-demand PWL models.
From a PI perspective, there are three things you care about: efficiency, sufficiency, and stability. The ability to perform accurate AC analysis to ensure that the impedance of the VRM, PDN, and loads are well matched assures efficiency. The ability to perform accurate DC analysis to ensure that all components are supplied with the power they need assures sufficiency. And the ability to perform full-system power ripple analysis assures stability.
At the end of the day, what this really means is that you now have the ability to shift-left system-level PI analysis all the way to the evaluation phase. It provides a platform that allows you to figure things out much earlier and to make better decisions with respect to design aspects associated with interposers and packages and boards. And all this allows you to create robust designs that will pass through signoff verification as quickly and painlessly as possible, thereby speeding time to market (TTM) and time to revenue (TTR).
Brad Griffin is a product management group director for the Multiphysics System Analysis Group at Cadence Design Systems, Inc., and the author of The System Designer’s Guide to… System Analysis (a free eBook available for download).
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