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Does Copper Pour on a Signal Layer Decrease Signal-To-Signal Isolation?
April 7, 2022 | Steve Hageman, Analog HomeEstimated reading time: 1 minute

Does putting a ground pour on PCB signal layers make the isolation better or worse? It can go either way, but with the proper knowledge and application, this technique will improve your designs.
In this article, I’ll discuss how to simulate trace-to-trace isolation with true electromagnetic simulation software. We’ll also cover a variety of rules of thumb that can help you stay away from trouble.
Fact or Fiction?
Recently an acquaintance told me, “I have heard that putting a copper pour on a signal layer between traces actually makes the isolation between the traces worse.” I grabbed one of my RF boards and said, “If that is so, then how do all these RF boards that I have done with co-planar waveguide over ground manage to function? They all have copper pours on the signal layer, and they work to very high frequencies.”
Since co-planar waveguide over ground (CPWG), which is essentially “pouring copper on a signal layer,” is used for a lot of RF work, and is proven to work for very high-performance RF circuits, how did this contradictory opinion catch on in the industry?
To investigate this, I used a one-inch section of 50-ohm microstrip consisting of an aggressor trace from ports 1 to 2 and a victim trace running in parallel from ports 3 to 4. I used typical values for the dimensions as might be on a real PCB. The trace width is 20 mils, with a spacing of 60 mils from center to center, over an FR-4 substrate, 9.5 mils thick, with a modeled Er of 4.4.
To read this entire article, which appeared in the March 2022 issue of Design007 Magazine, click here.
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Connect the Dots: Stop Killing Your Yield—The Hidden Cost of Design Oversights
04/03/2025 | Matt Stevenson -- Column: Connect the DotsI’ve been in this industry long enough to recognize red flags in PCB designs. When designers send over PCBs that look great on the computer screen but have hidden flaws, it can lead to manufacturing problems. I have seen this happen too often: manufacturing delays, yield losses, and designers asking, “Why didn’t anyone tell me sooner?” Here’s the thing: Minor design improvements can greatly impact manufacturing yield, and design oversights can lead to expensive bottlenecks. Here’s how to find the hidden flaws in a design and avoid disaster.
Real Time with... IPC APEX EXPO 2025: Tariffs and Supply Chains in U.S. Electronics Manufacturing
04/01/2025 | Real Time with...IPC APEX EXPOChris Mitchell, VP of Global Government Relations for IPC, discusses IPC's concerns about tariffs on copper and their impact on U.S. electronics manufacturing. He emphasizes the complexity of supply chains and the need for policymakers to understand their effects.
The Chemical Connection: Surface Finishes for PCBs
03/31/2025 | Don Ball -- Column: The Chemical ConnectionWriting about surface finishes brings a feeling of nostalgia. You see, one of my first jobs in the industry was providing technical support for surface cleaning processes and finishes to enhance dry film adhesion to copper surfaces. I’d like to take this opportunity to revisit the basics, indulge in my nostalgia, and perhaps provide some insight into why we do things the way we do them in the here and now.
NUS Physicists Discover a Copper-free High-temperature Superconducting Oxide
03/28/2025 | PRNewswireProfessor Ariando and Dr Stephen Lin Er Chow from the National University of Singapore (NUS) Department of Physics have designed and synthesised a groundbreaking new material—a copper-free superconducting oxide—capable of superconducting at approximately 40 Kelvin (K), or about minus 233 degrees Celsius (deg C), under ambient pressure.
AT&S Sets New Standards in the Recycling of Copper and Chemicals
03/25/2025 | AT&SAT&S has been working for years to reduce the ecological footprint of its production sites worldwide with a comprehensive sustainability strategy and considerable investments.