Cadence Wins Six 2022 TSMC OIP Partner of the Year Awards

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Cadence Design Systems, Inc. announced that it has won six Open Innovation Platform (OIP) Partner of the Year awards from TSMC for its EDA, IP and cloud solutions. Cadence was presented with awards for the joint development of the N3E design infrastructure, 3Dblox Design Solution, analog migration flow, RF design solutions, cloud-based productivity solution and DSP IP. In addition, Cadence was recognized as a founding member of the TSMC 3DFabric™ Alliance.

The awards and 3DFabric Alliance member recognition are based on the collaborative work with TSMC highlighted below:

• N3E Design Infrastructure: Cadence worked closely with TSMC to optimize the complete, integrated digital implementation and signoff flow and custom/analog flow for the TSMC N3E process technology to enable customers to achieve power, performance and area (PPA) targets and accelerate time to market.
• 3Dblox ™ Design Solution: The leading Cadence® Integrity™ 3D-IC platform achieved certification and met all reference flow criteria for TSMC’s 3DFabric offerings. In addition, the companies worked together to develop TSMC’s latest 3Dblox™ standard and Cadence’s Advanced Substrate Router (ASR) to help customers accelerate advanced multi-die package design.
• Analog Migration Flow: Cadenceworked with TSMC to develop a node-to-node process migration flow built upon the CadenceVirtuoso® design platform for custom/analog IC blocks that use TSMC’s advanced node technologies. The collaboration ensures that customers can automatically migrate a source design in a given TSMC N5 or N4 process to a new design on N3E process technology.
• RF Design Solutions: Cadenceand TSMC collaborated on an RF design reference flow to accelerate mmWave design projects that utilize the TSMC N16RF semiconductor technology for the creation of next-generation mobile and 5G applications.
• Cloud-Based Productivity Solution: Cadence expanded its cloud collaboration with TSMC by accelerating the physical verification of giga-scale digital designs via the Cadence Pegasus™ Verification System, which enables customers to speed design schedules and reduce compute costs.
• DSP IP: Cadence continued its collaboration with TSMC’s Soft IP9000 team to certify Cadence Tensilica® DSP IP in the TSMC integration flow.
• Founding Member of the TSMC 3DFabric Alliance: As a founding member, Cadence is working with TSMC to advance design and analysis innovation across emerging multi-chiplet-based technologies for hyperscale computing, mobile, 5G, and AI applications.

“Each year, the TSMC OIP Partner of the Year awards give us an opportunity to recognize our industry ecosystem for their outstanding work in design enablement,” said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “Through our longstanding collaboration with Cadence, we’ve continued to work tirelessly to ensure our customers can use our latest technologies to design with confidence and stay ahead of the competition in their respective markets.”

“We have a long history of collaborating with TSMC to deliver key innovations that accelerate the design process and enable customers to achieve time-to-market goals,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “These prestigious TSMC awards and our participation in the 3DFabric Alliance underscore our commitment to enabling SoC design excellence via our Intelligent System Design strategy, and we are looking forward to our customers leveraging our latest technologies to develop their innovative, next-generation products across a wide range of end markets.”