Cadence Announces 8533Mbps LPDDR5X IP Solution for Next-Gen AI, Automotive and Mobile Applications
December 23, 2022 | Cadence Design Systems, Inc.Estimated reading time: 1 minute

Cadence Design Systems, Inc. announced the first LPDDR5X memory interface IP design optimized to operate at 8533Mbps—up to 33% faster than the previous generation of LPDDR IP. Available now for customer engagements, the Cadence® LPDDR5X IP boasts a new high-performance, scalable and adaptable architecture based on Cadence’s proven and highly successful LPDDR5 and GDDR6 product lines. The new Cadence LPDDR5X memory IP solution consists of a silicon-proven PHY and high-performance controller designed to connect to LPDDR5X DRAM devices that follow the JEDEC JESD209-5B standard. The controller/PHY interface is based on the latest DFI 5.1 specification, and a variety of on-chip buses are supported.
LPDDR5X memory opens up a wide variety of high-bandwidth applications beyond the mobile market traditionally served by LPDDR memory, including advanced driver assistance systems (ADAS), autonomous driving, lower-end edge AI and networking. Cadence LPDDR5X IP is designed to enable the industry’s next-generation SoC designs for these and other applications with flexible floorplan design options, while the new architecture allows fine-tuning of power and performance based on individual application requirements.
Cadence design IP supports the fastest data rate defined by the JEDEC standard (JESD209-5B). Cadence’s LPDDR5X Controller and PHY have been verified with Cadence’s Verification IP (VIP) for LPDDR5X to provide rapid IP and SoC verification closure. Cadence VIP for LPDDR5X includes a complete solution from IP to system-level verification with DFI VIP, LPDDR5X memory model and System Performance Analyzer.
“LPDDR5X’s peak speeds will raise the bar for device experiences and performance at the edge, from automotive to consumer IoT to networking devices,” said Michael Basca, vice president of products and systems in Micron’s Embedded Business Unit. “Our collaboration with Cadence will accelerate ecosystem adoption of LPDDR5X by enabling the next wave of chipsets to work seamlessly with this low-power, high-performance memory.”
“Cadence LPDDR5X IP operating at 8533Mbps in silicon showcases Cadence’s next-generation architecture for complete memory system IP solutions,” noted Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. “This new leading-edge memory IP solution solidifies our memory interface IP leadership by enabling the industry’s future AI, automotive and mobile SoC designs today.”
The LPDDR5X IP supports Cadence’s Intelligent System Design™ strategy, which enables SoC design excellence with high-performance, design-optimized, best-in-class technology.
Testimonial
"In a year when every marketing dollar mattered, I chose to keep I-Connect007 in our 2025 plan. Their commitment to high-quality, insightful content aligns with Koh Young’s values and helps readers navigate a changing industry. "
Brent Fischthal - Koh YoungSuggested Items
Mouser Electronics Celebrates Its 2025 Best-in-Class Award Winners
10/01/2025 | BUSINESS WIREMouser Electronics, Inc., the New Product Introduction (NPI) leader™ empowering innovation, is pleased to announce the 2025 recipients of the Mouser Best-in-Class Awards.
Elementary Mr. Watson: Chasing Checkmarks, Not Signal Integrity
10/01/2025 | John Watson -- Column: Elementary, Mr. WatsonFor the September 2025 issue of Design007 Magazine on signal integrity, I explored how the PCB is similar to a military obstacle course: walls that sap energy like impedance mismatches, barbed wire that cuts like crosstalk, and mud pits that drag a signal down like attenuation. The takeaway was clear that a PCB is not a flat drawing; it's an electromagnetic ecosystem filled with hazards that test every signal that dares to cross it. The real danger lies not in the obstacles themselves, but in the fact that many designers never see them.
Target Condition: Rethinking the PCB Stackup Recipe
10/01/2025 | Kelly Dack -- Column: Target ConditionMarie Antoinette is attributed with saying, “Let them eat cake,” but historians now agree she likely never said it. It was probably revolutionary propaganda to paint her as out of touch with the starving masses. Yet, the phrase still lingers, and oddly enough, it applies to the world of PCB design.
Connect the Dots: Evolution of PCB Manufacturing—Lamination
10/02/2025 | Matt Stevenson -- Column: Connect the DotsWhen I wrote The Printed Circuit Designer's Guide to...™ Designing for Reality, it was not a one-and-done effort. Technology is advancing rapidly. Designing for the reality of PCB manufacturing will continue to evolve. That’s why I encourage designers to stay on top of the tools and processes used during production, to ensure their designs capitalize on the capabilities of their manufacturing partner.
Siemens, ASE Collaborate on Workflows for ASE’s VIPack Advanced Packaging Platform
09/25/2025 | SiemensSiemens Digital Industries Software announced that it is collaborating with Advanced Semiconductor Engineering, Inc. (ASE), the leading global provider of semiconductor manufacturing services in assembly and test, to develop 3Dblox-based workflows for the ASE VIPack™ platform using Siemens’ Innovator3D IC™ solution, which is fully certified for the 3Dblox standard..