Cadence Announces 8533Mbps LPDDR5X IP Solution for Next-Gen AI, Automotive and Mobile Applications
December 23, 2022 | Cadence Design Systems, Inc.Estimated reading time: 1 minute
Cadence Design Systems, Inc. announced the first LPDDR5X memory interface IP design optimized to operate at 8533Mbps—up to 33% faster than the previous generation of LPDDR IP. Available now for customer engagements, the Cadence® LPDDR5X IP boasts a new high-performance, scalable and adaptable architecture based on Cadence’s proven and highly successful LPDDR5 and GDDR6 product lines. The new Cadence LPDDR5X memory IP solution consists of a silicon-proven PHY and high-performance controller designed to connect to LPDDR5X DRAM devices that follow the JEDEC JESD209-5B standard. The controller/PHY interface is based on the latest DFI 5.1 specification, and a variety of on-chip buses are supported.
LPDDR5X memory opens up a wide variety of high-bandwidth applications beyond the mobile market traditionally served by LPDDR memory, including advanced driver assistance systems (ADAS), autonomous driving, lower-end edge AI and networking. Cadence LPDDR5X IP is designed to enable the industry’s next-generation SoC designs for these and other applications with flexible floorplan design options, while the new architecture allows fine-tuning of power and performance based on individual application requirements.
Cadence design IP supports the fastest data rate defined by the JEDEC standard (JESD209-5B). Cadence’s LPDDR5X Controller and PHY have been verified with Cadence’s Verification IP (VIP) for LPDDR5X to provide rapid IP and SoC verification closure. Cadence VIP for LPDDR5X includes a complete solution from IP to system-level verification with DFI VIP, LPDDR5X memory model and System Performance Analyzer.
“LPDDR5X’s peak speeds will raise the bar for device experiences and performance at the edge, from automotive to consumer IoT to networking devices,” said Michael Basca, vice president of products and systems in Micron’s Embedded Business Unit. “Our collaboration with Cadence will accelerate ecosystem adoption of LPDDR5X by enabling the next wave of chipsets to work seamlessly with this low-power, high-performance memory.”
“Cadence LPDDR5X IP operating at 8533Mbps in silicon showcases Cadence’s next-generation architecture for complete memory system IP solutions,” noted Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. “This new leading-edge memory IP solution solidifies our memory interface IP leadership by enabling the industry’s future AI, automotive and mobile SoC designs today.”
The LPDDR5X IP supports Cadence’s Intelligent System Design™ strategy, which enables SoC design excellence with high-performance, design-optimized, best-in-class technology.
Suggested Items
Happy’s Tech Talk #28: The Power Mesh Architecture for PCBs
05/07/2024 | Happy Holden -- Column: Happy’s Tech TalkA significant decrease in HDI substrate production cost can be achieved by reducing the number of substrate layers from conventional through-hole multilayers and microvia multilayers of eight, 10, 12 (and more), down to four. Besides reducing direct processing steps, yield will increase as defect producing operations are eliminated.
Hirose Launches Solution Partner Network to Address Changing Design Challenges
05/06/2024 | HiroseHirose, a leader in the design and manufacturing of innovative connector solutions, has established a Solution Partner Network that enables OEMs to quickly explore product design, specialty IP, and component fulfillment options that best suit their needs.
New Yorker, Major League Electronics Sign New Franchised Distribution Agreement
05/06/2024 | New Yorker Electronics Co.New Yorker Electronics, global distributor of electronic components, recently announced a new franchised distribution agreement with Major League Electronics, renowned manufacturer of interconnect products.
I-Connect007 Editor’s Choice: Five Must-Reads for the Week
05/03/2024 | Nolan Johnson, I-Connect007This week’s most important news is strategic—and telling. When one puts together the IPC industry reports, we simply have to include the recent conversation with Shawn DuBravac and Tom Kastner. On the design side, check out the latest “On The Line With…” podcast featuring Brad Griffin from Cadence Design Systems, discussing SI and PI in the realm of intelligent system design.
Synopsys, Samsung Electronics Collaborate to Achieve First Production Tapeout of Flagship Mobile CPU
05/03/2024 | PRNewswireSynopsys, Inc. announced that Samsung Electronics has achieved successful production tapeout for its high-performance mobile SoC design, including flagship CPUs and GPUs, with 300MHz higher performance using Synopsys.ai™ full stack AI-driven EDA suite and a broad portfolio of Synopsys IP on Samsung Foundry's latest Gate-All-Around (GAA) process technologies.