Estimated reading time: 17 minutes

Happy’s Tech Talk #22: Computer-aided Bare Board Testing, Revisited

This is from a paper I gave at an IPC conference in Denver in 1983. Obviously, computers have come a long way since 1983, so the minicomputer I discuss using here can easily be replaced by a simple desktop or notebook computer. The statistics are from Dr. W. Edwards Demings’ first book and the software used is from NIST’S Engineering Statistics Handbook. It’s still very appropriate.

Even though I speak in the present tense in the paper, I am talking about 1983; much of what is discussed here is related to the industry from the early 1970s through 1983.

Introduction
Over the past decade, Hewlett-Packard (HP) increased the performance, capability, sophistication of its products, and the PCB multilayers it contains in their complexity. One of the results of this trend has been the increasing use of high density multilayer printed circuit boards, so the ability to find electrical opens and shorts through a visual inspection process has declined to the point that now it has become impossible. Today, many PC manufacturers view bare board electrical test as unavoidable, and few perform any type of defect analysis to see why boards fail this test. HP’s Sunnyvale Printed Circuit Facility (SPCF) set out to exploit the information potential of the board test process.

Continuity testing occurs when a printed circuit is approximately 85% completed. Testing supplements PCB visual inspection, which was the only prior means for finding opens and shorts. The current average electrical defects at first test are reported in the HP PC Manufacturing Standards, Section 407 (Raw Board Electrical Test). This section has details on HP's Electrical Test Standards. This includes when to test, test extent, electrical characteristics, and fixture documentation specification. The development of this standard has gone a long way in eliminating the uncertainty and unknowns with our (HP’s) customers. The criteria of when to test a bare board is now a simple equation.

When to Test
The debate on when, how much, and how often to electrical test bare PCBs ended when Dr. W. Edwards Deming provided insight into the test and inspection question. In chapter 8 of his manual, "On the Management of Statistical Techniques for Quality and Productivity," he outlined the equations below. The essential elements in the decision are the average electrical defect, the cost to test one unloaded PC board, and the cost to test and repair it if a defected board is loaded. Estimates on the average defects are shown in Figures 1 and 2.

The following (provided by Dr. Deming to HP) are developed to minimize the average total cost of a lot.

(1)    The average cost of inspection of a lot of N parts is Y1,

Y1 = N ( P+Q x ) k1 / q where x =¹

(2)    The loss from ( N-n ) Q p defective parts that get into the production line is Y2,

Y2 = N ( 1-x ) Q p ( k2 + k1/q )

(3)    The average total cost per lot will be Y = Y1 + Y2.

Y = (N k1 / q) [1+Q q ( kp-1) (1- x)] where K = ( 3).

1.       If Kp < 1, we have minimum Y if n=0: Therefore, no inspection or test.

(This is the cost to inspect and correct the final product, Np [k2 + k1/q].)

2.       If Kp > 1, we have minimum Y if n = N: Therefore, 100% inspection or test.

(This is the cost to test all bare boards, Nk1/q.)

The two conditions of n=0 or no testing, and n=N or 100% testing can be plotted in Figure 3. This is the curve of Kp=1, the point of indifference. It is the values of p and the reciprocal of p, 1/p=k2/k1. By calculating the ratio k2/k1 and estimating p, any point above the curve in Figure 3 represents the need to electrical test. Below the curve, no testing is required.

Notations:

N = Number of pieces in a lot

n = Number of pieces in a sample from lot

p = Average fraction defective

q = 1 - p

k1 = The cost to test one unloaded PC board

k2 = The cost of a defective piece that gets into the production line. Includes the cost to discover that this is the defective part, non-recoverable parts, and the cost to replace the PC assembly as well as to retest the replaced assembly.

P = Proportion of lot set off for screening (testing)

Q = 1  -P

How Much to Test
Test extent for dedicated fixturing: The most thorough test of a printed circuit board is to check for all possible shorts and to verify there are no open traces on the board. Checking for shorts requires a minimum of one probe on each circuit network. Checking traces for opens requires a minimum of two probes for each trace. An opens test will usually have more probes to verify every end of a network.

Since the cost of fixturing is directly proportional to the number of probes in a test fixture, the most thorough test also requires the most expensive fixturing. The following table defines general criteria for the types of tests to be performed for dedicated fixtures.

Test level 1 is a bare minimum test but for use only when opens are improbable. Test level 2 is the minimum recommended test level. Test level 3 is the most desirable as it evaluates all shorts and opens at lowest cost. Tests 4 and 5 pinpoint the trouble spot to a smaller area. Refer to Figure 4 for examples of test point locations for the different test extents.

No Testing
If there is no electrical test in a PC shop, the visual inspection area is burdened with trying to find electrical opens and shorts. As PCBs continue to become denser, with closer spacings, more layers, and smaller traces, opens and shorts become more common and finding them through visual inspection gets harder. The most obvious benefit of implementing electrical test is that it allows visual inspection people to concentrate on specification tolerances and cosmetic defects, which gives the PCB manufacturer a marked productivity increase in that area of his shop.

When a PCB customer buys boards untested and does not do a bare board test of his own, it is difficult at best for him to identify defects in the boards. This is usually attempted in a pretest area after the boards have been loaded with components, and it is complicated by his not being able to see the board under the components, the possibility of bad components, and the processes such as wave solder that the boards have been put through. Suffice it to say that all but a small minority of defective boards end up being scrapped (components included) with too much time having been invested in them while trying to get them to work. So, no one's the wiser? Probably not for long.

Customer Testing
Most PCB customers are well aware of the "Japanese Scenario” wherein all components of a product (including PCBs) are tested prior to assembly so there is very little troubleshooting, repair, or rework investment. This is what the customer wants. A second aspect of the scenario is that of process feedback, wherein, when a part fails a test, an engineer immediately researches the cause, and fixes it upstream so it does not happen again. This is what the PCB manufacturer needs to improve his yield. Let us keep both aspects of the scenario in mind and look at what happens when a customer buys a bare board test system (because the PC manufacturer doesn't have one).

This is a self-perpetuating circle. The circle is detrimental because:

• There is a good possibility that the artwork the manufacturer was given to build the boards with, or one of his upstream processes, is somewhat out of spec. This means that the defective features get included in the boards somewhat regularly.
• The manufacturer first learns that a percentage of a PCB run failed when his customer calls to order more, as soon as possible. Scheduling is disrupted by another hot order.
• Depending on distances involved, board volumes, and return for credit processing delays, the manufacturer may always be one or more runs behind in finding out what went wrong.
• Unless the test error printouts attached to returned boards show a blatant correlation, research into defect causes requires a time-consuming correlation of errors by hand. The manufacturer probably cannot spare the labor because hot orders are coming through.
• The customer test circle is bad for public relations. The customer sees all process problems before the manufacturer has a chance to rework and alleviate them.
• The manufacturer has no control over the customer’s testing. Some of the boards being returned may actually be good but were failed because of sticking or bent pins in the test system and fixture.
• A testing operation needs troubleshooting feedback to insure valid test results. A troubleshooting (and repair) operation needs retest feedback to ensure that repairs are effective. In the customer test circle, there is so much time and red tape between these operations that neither function well.

From the above, we can see that customer testing implies that the PCB manufacturer can only implement process feedback in a fashion that is too late with dubious data in an inconvenient format (i.e., old error printout). Progress begins when a test system is brought in-house.

In-house Testing to Raise Yield and Productivity
It will be helpful to think of process feedback as a constant endeavor to tune up and fine tune upstream processes and tools by learning from your mistakes. Yield improves when you quit making the same mistakes. Productivity improves in relation to yield.

The key to effective feedback is information; the fact that an electrical test (ET) operation rejects more boards than any other process is simply an indication of this information potential. The development efforts at SPCF toward exploiting ET information began due to needs in the ET area itself.

Getting Started
Now the testing happens in-house. Visual inspection is no longer a bottleneck, customers are happy, and the test and troubleshooting areas are complementing each other. However, how do you use ET information to find why the bad boards failed, when you already seem to spend too much time finding a good board?

Bare board test systems operate by comparing the electrical connections of a board being tested, with a memory representation of the connections in a "good board.” Finding this idealistic "good board" can be a problem, especially for complex PCBs that will eventually show a 30% or higher failure rate. The amount of time spent in the "find a good board" mode directly depends on how often new part numbers and revisions are tested, the complexity (and hence the yield) of these new boards, and the data reduction capabilities that are available.

To give an example, we will assume that the self-learn mode of the test system is used to program the connections in a board sitting on the top of the stack to be tested. Next, the system is placed in the test mode and, say, 10 boards are tested, only to find that each of them shows an appalling number of errors. A perceiving question at this point is, “Just how often are each of these errors occurring?"

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