Knocking Down the Bone Pile: Gold Mitigation for Class 2 Electronics
Punching Out: Your Financial Preparation for a Sale
Nolan's Notes: The Next Killer App in Component Manufacturing
Cadence Wins Four 2023 TSMC OIP Partner of the Year Awards
October 20, 2023 | Cadence Design Systems, Inc.Estimated reading time: 2 minutes
Cadence Design Systems, Inc. announced that it has won four Open Innovation Platform® (OIP) Partner of the Year awards from TSMC for its EDA and IP design solutions. Cadence was presented with awards for the joint development of the N2 and N3P design infrastructure, 3Dbloxdesign prototyping solution, mmWave design solutions and DSP IP. The awards build upon the companies’ long-standing history of collaboration that has delivered many highly innovative SoC and advanced packaging design solutions to the global market.
The awards are based on the following TSMC collaborations:
- N2 and N3P Design Infrastructure: Cadence optimized its complete digital and custom/analog flows for the TSMC N2 and N3E process technologies to help customers achieve power, performance and area (PPA) goals and accelerate innovation. Additionally, Cadence’s AI-powered solutions, Cadence® Cerebrus™ Intelligent Chip Explorer and Virtuoso® Studio, support these nodes, offering customers innovative automation capabilities to make them more efficient.
- Joint Development of 3Dblox Design Prototyping Solution: Design flows based on the Cadence Integrity™ 3D-IC Platform support the TSMC 3Dblox standard for 3D front-end design partitioning in complex systems. The flows include system prototyping flows, which are optimized for all of TSMC’s latest 3DFabric™ offerings, including Integrated Fan-Out (InFO), Chip-on-Wafer-on-Substrate (CoWoS®) and System-on-Integrated-Chips (TSMC-SoIC® ) technologies.
- Joint Development of mmWave Design Solutions: The new Cadence Virtuoso Studio was integrated into the TSMC N16 mmWave RF design reference flow and N6RF design reference flow, and support has been added for the N4P RF design reference flow. In addition, Cadence collaborated with TSMC to optimize the Virtuoso platform for the 79GHz mmWave design reference flow on TSMC’s N16 process.
- DSP IP: Cadence expanded its collaboration with TSMC’s Soft IP9000 team to certify Cadence Tensilica® DSP IP in the TSMC integration flow.
“TSMC works continuously with our OIP design partners to enable technology advancements that make it faster and easier for customers to deliver competitive designs to market, simpler for customers to adopt our solutions,” said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “Cadence’s commitment to design excellence is exemplary, and the TSMC OIP Partner of the Year awards are a testament to their dedication to ongoing innovation.”
“By continuing to collaborate closely with TSMC, we’re constantly energized by the innovations our customers bring to life using our technologies,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “It’s an honor to be recognized with these prestigious TSMC awards, and they are a testament to the work we’ve done to enable our customers to achieve their design and time-to-market goals.”
Share on:
Suggested Items
RF PCB Design Tips and Tricks
05/08/2025 | Cherie Litson, EPTAC MIT CID/CID+There are many great books, videos, and information online about designing PCBs for RF circuits. A few of my favorite RF sources are Hans Rosenberg, Stephen Chavez, and Rick Hartley, but there are many more. These PCB design engineers have a very good perspective on what it takes to take an RF design from schematic concept to PCB layout.
Cadence Unveils Millennium M2000 Supercomputer with NVIDIA Blackwell Systems
05/08/2025 | Cadence Design SystemsAt its annual flagship user event, CadenceLIVE Silicon Valley 2025, Cadence announced a major expansion of its Cadence® Millennium™ Enterprise Platform with the introduction of the new Millennium M2000 Supercomputer featuring NVIDIA Blackwell systems, which delivers AI-accelerated simulation at unprecedented speed and scale across engineering and drug design workloads.
The Right Blend: Mixed Wireless Technologies
05/08/2025 | Kirsten Zima, Siemens EDAA common trend recently is to employ as many radios as possible on a single PCB. With the increase of wireless standards and the downscaling of PCB size, it can be difficult to know what the most critical design parameters are to focus on. In this article, we’ll discuss the most important considerations to make when designing with mixed wireless technologies, such as Bluetooth, GPS, and Wi-Fi, on a single PCB. These considerations include antennas, frequencies, FCC compliance, shielding, and layout with and without transition vias.
ZESTRON Announces New Reliability and Solutions Service for Risk Assessment & Mitigation of Electronic Assemblies
05/06/2025 | ZESTRONZESTRON, the leading global provider of high-precision cleaning products, services, and training solutions, is thrilled to introduce its new Reliability and Solutions (R&S) service.
PCB East Continues to Expand
05/06/2025 | Andy Shaughnessy, Design007 MagazineIt was a perfect week for a conference and trade show in metropolitan Boston, with high temperatures in the 70s. PCB East took place at the Boxboro Regency Hotel and Conference Center April 29–May 2, with the expo on April 30. PCB East has been expanding since its relaunch a few years ago, with conference and show attendance rising each year.