Cadence Signoff Solutions Empower Samsung Foundry’s Breakthrough Success on 5G Networking SoC Design
December 1, 2023 | Cadence Design Systems, Inc.Estimated reading time: 2 minutes
Cadence Design Systems, Inc. announced that Samsung Foundry successfully taped out a 5G networking SoC design on the Samsung 5LPE technology using the Cadence® Quantus™ Extraction Solution and Tempus™ Timing Solution. This accomplishment marks a turning point for Samsung Foundry where the team deployed the Cadence signoff solutions for the first time, achieving a 2X productivity boost that led to faster design closure versus its previous design methodology. The team also experienced significant power, performance and area (PPA) gains on this 120M instance design using the Cadence integrated flow.
One of the most notable aspects of Samsung Foundry’s achievement was the team’s use of the Tempus ECO Option within the Cadence Innovus™ Implementation System, which facilitated faster design convergence and closure, leading to an unprecedented reduction in project timeline. Further contributing to the productivity improvement, Samsung Foundry deployed the Tempus hierarchical static timing analysis feature, enabling hierarchical design closure while optimizing resource allocation and reducing machine and memory demands. Lastly, the Samsung team utilized Tempus and Quantus distributed technology to curtail the overall runtime for this complex design.
“The successful tapeout of our SF5A design for 5G networking was a significant milestone for our team, and the enhanced efficiency and reduced runtime afforded by the Cadence Quantus Extraction Solution and Tempus Timing Solution are a testament to the power of innovation and collaboration between the Cadence and Samsung teams,” said Sangyun Kim, Vice president and head of Foundry Design Technology Team at Samsung Electronics. “We’re committed to pushing the boundaries and leveraging the effectiveness of these signoff tools to deliver our designs to market faster, and we look forward to building upon our success for future projects and advancements.”
“The integrated Quantus Extraction Solution and Tempus Signoff Solution played a pivotal role in enabling Samsung Foundry to achieve enhanced productivity and PPA gains and time-to-market efficiencies,” said Vivek Mishra, corporate vice president in the Digital & Signoff Group at Cadence. “The most rewarding aspect of the collaboration with Samsung Foundry was seeing the team achieve their target design metrics while accelerating the time to market. We’re looking forward to continuing our work together to advance innovation.”
The Quantus Extraction Solution and Tempus Timing Solution are part of the broader Cadence digital full flow, offering a faster path to tapeout. The tools and flow support the company’s Intelligent System Design™ strategy, enabling customers to achieve SoC design excellence.
Suggested Items
Flexible Circuit Technologies Welcomes Regional Business Development Manager Derek Rossberg
07/15/2025 | Flexible Circuit TechnologiesFlexible Circuit Technologies a Minnesota-based flexible circuit and advanced electronics contract manufacturer, welcomes Derek Rossberg as Regional Business Development Manager.
Digital Twin Concept in Copper Electroplating Process Performance
07/11/2025 | Aga Franczak, Robrecht Belis, Elsyca N.V.PCB manufacturing involves transforming a design into a physical board while meeting specific requirements. Understanding these design specifications is crucial, as they directly impact the PCB's fabrication process, performance, and yield rate. One key design specification is copper thieving—the addition of “dummy” pads across the surface that are plated along with the features designed on the outer layers. The purpose of the process is to provide a uniform distribution of copper across the outer layers to make the plating current density and plating in the holes more uniform.
Meet the Author Podcast: Martyn Gaudion Unpacks the Secrets of High-Speed PCB Design
07/10/2025 | I-Connect007In this special Meet the Author episode of the On the Line with… podcast, Nolan Johnson sits down with Martyn Gaudion, signal integrity expert, managing director of Polar Instruments, and three-time author in I-Connect007’s popular The Printed Circuit Designer’s Guide to... series.
Showing Some Constraint: Design007 Magazine July 2025
07/10/2025 | I-Connect007 Editorial TeamA robust design constraint strategy balances dozens of electrical and manufacturing trade-offs. This month, we focus on design constraints—the requirements, challenges, and best practices for setting up the right constraint strategy.
The Shaughnessy Report: Showing Some Constraint
07/14/2025 | Andy Shaughnessy -- Column: The Shaughnessy ReportWhen we first decided to cover strategies for setting PCB design constraints, one designer we spoke with said, “They’re not really constraints; they’re more like guardrails that prevent your design from going off a cliff.”