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Designer’s Notebook: What Designers Need to Know About Manufacturing, Part 2

The printed circuit board (PCB) is the primary base element for providing the interconnect platform for mounting and electrically joining electronic components. When assessing PCB design complexity, first consider the component area and board area ratio. If the surface area for the component interface is restricted, it may justify adopting multilayer or multilayer sequential buildup (SBU) PCB fabrication to enable a more efficient sub-surface circuit interconnect.

Developing the circuit board to accommodate surface mount passive and the various semiconductor package families, the designer and assembly process engineer must respect the disciplines, capabilities, and limitations within each other’s realm. Additionally, each must be cognizant of the industry-developed standards and tolerances that control IC packaging and the requirements established by the industry for reliably attaching these devices to the printed circuit board.

The three primary PCB commodities being fabricated:

1. Single-sided circuits have a copper circuit pattern on only one side and can accommodate both SMT component mounting and through-hole components that are mounted onto the opposite surface, with their terminals protruding through mechanically drilled holes for termination. The single-sided circuit boards are generally for less complex and/or cost-sensitive applications.

2. Double-sided circuits will rely on copper-plated holes for interconnecting conductor patterns between opposing circuit layers. For surface mount applications, component land patterns are incorporated into the design to enable solder attachment. Land patterns for surface-mounted components may be furnished on one or both sides.

3. Multilayer circuits will rely on copper-plated holes for interconnecting the outer layer conductor patterns and the inner layer conductor patterns. Typical of the less complex two-sided PCB, surface mount component land patterns may be incorporated into the design to enable solder attachment on one or both sides of the circuit board.

Providing a Copper Balanced PCB Structure
The most desirable PCB construction is one where copper layers are built up in pairs and arranged symmetrically about the core of the board: two, four, six, eight, and so on. The various pre-etched circuit layers will be assembled and aligned with partially cured prepreg material between layers, as compared in Figure 1.

The sequence in which the circuit board layers are assembled (signal, power, ground, etc.) is a key factor that will affect signal transmission performance. In addition to performance concerns, controlling fabrication cost should be a priority as well. Layer count and the method selected for interconnecting between circuit layers, for example, will have significant influence in controlling process complexity. Implementing blind microvia technology for layer-to-layer interconnect will enable significantly greater circuit routing density, but the build-up process has substantial impact on the manufacturing complexity since it will affect the number of lamination cycles. Any layer on which a microvia begins or ends requires a sub-construction, and each sub-construction will require an extra lamination cycle. Some of the more complex sequential buildup (SBU) multilayer designs will require several lamination cycles, and with each lamination cycle, the core or base materials will also be subjected to repeated exposure to elevated temperatures and high pressure. The concern is that excessive lamination cycles can contribute to base material decomposition.

Stacked and Staggered Microvias: Pros and Cons
Two variations of microvia stacking are commonly employed: offset via stacking and vertical via-on-via stacking (Figure 2). Multilayer SBU circuit boards can use the vertically stacked microvia format when routing channels are restricted, or when the subsurface circuit layers are less restricted, the staggered microvia that offsets the blind via hole’s position from one layer to the nex, is recommended.

Stacking microvia holes directly in line with one another will simplify circuit routing during the CAD development process, but additional plating process steps to fill and planarize the resulting via cavities will impact fabrication throughput. When implementing vertically aligned microvias, each stage of the lamination sequence will require that the depression in the center of the microvia be plated flush with the surface of the copper conductor’s surface before lamination of the next circuit layer. Circuit fabricators note that providing a stable copper-to-copper interface between the filled microvia levels may be at risk when subjected to long-term physical or thermal stresses. When clustered together (fine-pitch array type semiconductor package interconnect, for example), thermal cycle testing of the in-line, vertically stacked microvia holes exhibited positive results.

Note: Studies conducted by Summit Interconnect found after extensive thermal test evaluation that the clustered, three-stack direct via-to-via interface format, typically required for fine-pitch array configured components, proved to be reliable.

Although the staggered three-level microvia will require slightly more surface area than the vertically stacked alternative, circuit board fabricators prefer the offset microvia option for circuit interconnect when vias are distributed randomly on the circuit board because the multilayer lamination sequence requires fewer process steps. With the microvias arranged in the staggered format, the copper fill operation is eliminated, saving both time and process complexity.

For both vertically stacked and staggered via-in-land component attachment sites on the circuit board’s outer layer(s), an additional copper plating step will be necessary to fill microvias flush with the land pattern’s surface to negate potential void formation in the solder interface during assembly processing.

High Density Conductor Routing
Conductor routing protocols must be established in advance. Adapting blind and buried microvia holes and furnishing pre-defined routing channels will help the circuit board designer to facilitate efficient routing of these often very fine-pitch and array terminal configured semiconductor packages. To aid the designer in establishing copper conductor width and spacing for circuit routing, IPC-2226 has defined three HDI circuit board complexity levels (Table 1) for both external and internal locations.

The space separating via-hole lands, microvia lands, and/or component attachment lands is referred to as channel width. The channel widths for routing array-configured semiconductors can easily be mathematically calculated using the terminal pitch (center-to-center distance), overall land pattern size, and the width and spacing established for conductors. This will provide the maximum number of conductors that can be routed between each channel (conductors per channel). When the surface channels are not wide enough to facilitate the conductor routing, the designer will need to consider reducing the conductor width and spacing on the circuit board surface or resort to sub-surface circuit routing to achieve interconnect.

Note: Whenever possible, to reduce bow and twist and to increase dimensional stability, conductor routing density should be uniformly distributed throughout the printed circuit board’s layer structure, and conductor density should be balanced within individual layers.

Supplier Assessment and Process Refinement
Know your PCB supplier and their capabilities; you don’t want to end up designing a board that can’t be manufactured. In addition to the design guidelines furnished in IPC-2221 and IPC-2222 for rigid circuit boards, suppliers will often publish their own design rules. To ensure a successful outcome for the circuit board design, it will be important that the designer recognize the manufacturing process complexities and become familiar with the circuit fabrication supplier’s technical capability. But before committing to adopting HDI or UHDI technology, the designer should confirm that the PCB supplier(s) selected can furnish the preferred complexity level at the anticipated production quantity.

Many OEM companies have already established a business relationship with their primary circuit board suppliers and have qualified their level of expertise and capability. Review your PCB suppliers’ material offerings:

• Discuss any unique base material or copper foil needs
• Clarify layer stacking alternatives with the supplier
• Define power and ground distribution objectives
• Specify controlled impedance requirements

When estimating the circuit board’s manufacturing cost, the designer must consider materials, circuit density, the number of circuit layers, and fabrication process complexity. While mechanically drilled and plated via holes are a mature technology for multilayer circuit board fabrication, the buried via and laser-ablated blind microvia hole forming requires more sophisticated systems.

This column originally appeared in the April 2024 issue of Design007 Magazine.

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