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Designers Notebook: Implementing HDI and UHDI Circuit Board Technology

To accommodate new generations of high I/O semiconductor packaging, circuit board technology has undergone significant changes in both the fabrication process method and the criteria for base material selection. The reason behind these changes is the new high-function semiconductor package families that require more terminals than their predecessors and a significantly narrower terminal pitch.

Interconnecting the very fine-pitch, high I/O semiconductors can dramatically affect the procedures used in both circuit board design and assembly processing. Implementation of circuit boards with higher interconnect density, however, will enable the seamless integration of high I/O semiconductor packages used in the more advanced electronic products. While a significant number of semiconductor packages will have a moderate level of complexity (I/O and terminal pitch), others may have an excessively high I/O density. One solution for solving conductor routing roadblocks is to adopt blind via-in-land techniques to transfer most of the interconnect responsibility to the circuit board's sub-surface layers typical of that illustrated in Figure 1.

Adapting blind and buried microvia holes and furnishing pre-defined routing channels will help the circuit board designer to facilitate efficient routing of these often very fine-pitch, array terminal-configured semiconductor packages.

Planning for Sequential Build-up (SBU) Processing
Sequential build-up processing offers a variety of design options. Circuit board designers can choose sequential build-up using stacked microvias for layer-to-layer interconnect, or the staggered microvia, where via-holes are offset from one layer to the other. The SBU circuit board’s complexity is ultimately determined by component density, circuit interconnect density, the number of signal conductor layers, and the number of layers dedicated to power and ground.

The sequence in which the circuit board layers are assembled (signal, power, ground, etc.) is a key factor that will affect signal transmission performance. In addition to performance concerns, controlling fabrication costs should be a priority as well. Layer count and the method selected for interconnecting between circuit layers, for example, will have a significant influence on controlling process complexity. Implementing blind microvia technology for layer-to-layer interconnect will enable significantly greater circuit routing density, but the build-up process has a substantial impact on the manufacturing complexity since it will affect the number of lamination cycles. Any layer on which a microvia begins requires a sub-construction with a perfectly aligned land pattern to complete the layer-to-layer via interface. A concern is that during each lamination cycle, the core materials are subjected to repeated exposure to elevated temperatures and high physical pressure that can contribute to material decomposition.

Controlling HDI and UHDI Fabrication Cost
The printed circuit board complexity level is determined by the number of signal and power/ground layers needed for interconnect. By adopting finer lines and spaces, small microvia holes, and innovative multilayer methods, the PCB designer will be able to overcome the many interconnect challenges posed by the newer generation semiconductors. When defining the complexity level for the HDI or UHDI circuit board, the designer will first establish a criterion for fabricating the circuit board. This will include the board outline and thickness limitation. In regard to controlling the specified circuit board thickness limit, a clear objective must be established to identify the number of circuit layers that are to be dedicated to signal routing and the number of layers reserved for power and ground distribution. While power and ground may require only two circuit layers, estimating the required number of signal layers will be determined by the component density and interconnect complexity.

When assessing printed circuit board design complexity, first consider the component area and board area ratio. If the surface area for component interface is restricted, it may justify adopting HDI multilayer fabrication. To assure a successful outcome for the HDI circuit board, it is important that the designer recognize the manufacturing process complexities and associated cost impact when implementing the more sophisticated fabrication procedures. Conductor routing protocols must be established in advance. The space separating via-hole lands, microvia lands and/or component attachment lands is referred to as “channel width.” The channel widths for routing array-configured semiconductors will be mathematically calculated using the terminal pitch (center-to-center distance) and the size of the land pattern. This provides the maximum number of conductors that can be routed between each channel (conductors per channel). When these channels are restricted further, the designer will need to consider sub-surface circuit routing to achieve interconnection.

Industry roadmaps consistently point to materials and process refinement as the key enablers for improving product performance and manufacturing efficiency. By addressing these concerns, the laminate industry has made significant refinements to all packaging and substrate-related materials. For HDI applications, the base structure selected must be mechanically stable enough to withstand the process temperatures experienced during board fabrication and throughout each phase of the assembly process. Regarding multilayer circuit board fabrication, although a mature and widely available service, each supplier’s process sequence and methods can vary. When component and circuit complexity require a higher circuit density solution, many circuit board fabricators have the expertise to furnish circuit boards that enable a higher-density circuit. There are, however, physical limits that often restrict the interconnect potential for the circuit board:

• Limited PCB surface area
• High ratio component density
• Greater semiconductor I/O
• Very fine-pitch terminal spacing

Implementing HDI technology has the potential to overcome most of the barriers associated with implementing the increasingly complex semiconductor products. The factors that define the limits of circuit interconnect routing ability on a circuit board include:

• Pitch/distance between via-holes or plated through-holes
• Number of conductors routed between land pattern features
• Established limit on the number of signal layers required

Most of the interconnect challenges can be solved by efficiently utilizing small-diameter micro via holes and more advanced multilayer fabrication methods.

HDI and UHDI Process Refinement
Process refinement for PCB manufacturing includes implementing more efficient imaging capability and greater utilization of alternative hole-forming techniques, applying more advanced etching and plating chemistry, and the refinement of lamination methods. The more technically competent PCB fabrication companies can produce conductors as narrow as 25 microns (~0.001") but they will rely on dielectric materials that are furnished with very thin copper foil. When conductor lines and space widths must be reduced further, the fabricator will likely utilize base materials prepared for a semi-additive copper plating process. While process proficiency for fabricating HDI or UHDI circuits will vary somewhat from one supplier to another, the examples shown in Table 1 compare the general process targets for subtractive, semi-additive, and fully-additive copper deposition and the process differences in microvia hole-forming methods.

A key contributor to enabling higher-density circuits is in the advances made in imaging technology. Laser direct imaging (LDI) and diode imaging systems have become mainstream technology for a wide segment of the PCB fabrication industry. While semi-additive circuit fabrication has enabled significantly finer circuit geometry, an alternative process is available from a relatively specialized supplier base that can furnish fully additive copper deposition to furnish even finer copper conductor geometry.

Supplier Communication
Developing the HDI or UHDI board is not a trivial endeavor. Materials and process complexities play a significant role in terms of manufacturability and the direct cost of fabricating multilayer circuit boards. The challenge here is to select the most suitable base materials for the application while meeting the end-product’s electrical and operating environment requirements. The best advice for the circuit board designer is to establish a dialogue with the circuit board fabrication specialist early on for each new design. Although a great deal of guidance for both high-density and sequential lamination circuit board designs are furnished in publications and IPC standards documents, the board supplier will ultimately be the designer’s most meaningful source for ensuring end-product satisfaction.

In regard to fabrication process efficiency and meeting the cost target for the circuit board, fabricators encourage the designer to evaluate the overall physical aspects of the circuit in order to simplify the design. For example, reducing conductor width and spacing will, as noted, significantly contribute to reducing layer count. As far as implementing SBU technology, the most expensive stackup configuration requires multiple sequential laminations. So, reducing the circuit layer stackup on each side of the board has a very positive impact on unit cost.

New Guidance Standards for HDI and UHDI Circuit Boards
IPC-2226 defines HDI as a printed circuit board with a higher wiring density per unit area than conventional PCBs. They have finer lines and spaces (≤100 µm/0.10 mm), smaller vias (<150 µm) and capture pads (<400 µm/0.40 mm), and higher connection pad density (>20 pads/cm2) than employed in conventional PCB technology. Ultra HDI PCBs are defined as products with conductor widths, isolation distances, and dielectric thicknesses under 50 µm, microvia diameters of less than 75 µm, and characteristics that exceed the existing IPC-2226 standard.

NCAB Group’s Jan Pedersen notes that his company “receives inquiries daily concerning printed circuit boards where the requirements for conductor widths and isolation distances are smaller than currently furnished on standard HDI boards.”

Pedersen initially served as chair of IPC’s medical committee, where they discussed the issue of newer requirements and parameters needed for future generations of semiconductor components that will require a much higher-density circuit board. The problem was that factories couldn’t build a printed circuit board when their customers didn’t have the ground rules for designing the circuit board. For the factories to be able to build their capacity, they would first need to base their manufacturing on standard compliance.

Discussions gradually evolved and eventually led to the approval of the IPC Technical Activity Executive Committee to form a technical working group of member companies to begin their work. After three years of planning by the group, two new documents, IPC-2229 and IPC-6019 for UHDI circuits, have evolved. These standards documents serve as a guide for printed circuit design engineers and manufacturers fabricating current and future high-density circuit boards. Their goal is to publish these documents near the end of 2025.

This column originally appeared in the October 2024 issue of Design007 Magazine.