Off Like a Rocket: A Review of the EIPC Summer Conference, Part 1

Estimated reading time: 14 minutes

Now on to the Technical Session
The technical session on next-generation PCB technology, capability developments, and standardisation was moderated by EIPC technical director Tarja Rapala-Virtanen and her first presenter was Stan Heltzel, who discussed advancing PCB technology for European space applications. He began his explanation of space mission requirements by describing the anatomy of a spacecraft in terms of a human body where PCBs are the nerves and veins of the spacecraft, providing a stable mechanical and thermal platform for the electrical interconnection of components. 

Quality was clearly of paramount importance. It began with design and came with a cost, although quoting Dr. Ralph Speth, “If you think good design is expensive, you should look at the cost of bad design.” 

Heltzel illustrated the extent and pace of technology development by comparing the guidance computer from an Apollo spacecraft with a currently available smartphone, which was a million times more powerful, weighed a hundred times less, and cost a thousand times less. A roadmap slide illustrated the trend in complexity of HDI structures. Current designs operating at a data rate of 56Gbps typically exhibit three stacked microvia layers and materials with spread-glass weave and smooth copper foil, with nickel-free finishes. 

He reviewed some failure modes, commenting that PCB reliability is particularly affected by thermo-mechanical stress in the z-direction and mentioning the interconnect stress test as a useful tool for outgoing inspection. Contamination could be the cause of many types of failure and Heltzel showed several case-study examples of intermittent and permanent failures. Contamination could be introduced by the raw materials supplier, but there is a higher risk during the lay-up process in PCB manufacture. He referred to Appendix A of IPC-4101E as specifying a better class of cleanliness of laminate and prepreg, by reinforcing acceptance criteria for surface and sub-surface imperfections. He also showed a case study example of the use of the temperature-humidity-bias test indicating breaches of insulation on inner-layer comb patterns. A further case-study example was the detection of contamination by high-resistance electrical testing to ECSS-Q-ST-70-60 at 250 volts and a 1 GΩ threshold. Dark field microscopy was used for evaluating dielectric integrity, including cracks, contamination and other types of inhomogeneity that might be located subsurface. It was clear that ESTEC has the benefit of comprehensive laboratory facilities.

Microvia reliability has been an area of ongoing concern, referencing IPC’s white paper on “The Hidden Reliability Threat,” with a European working group further investigating microvia reliability, led by ESA and Belgian research organisation IMEC. Recently, an ESA-led consortium achieved the first qualification of HDI PCBs for space missions, representing a major step forward in quality control. Heltzel described the collaborative project in detail: project objectives, test panel design and test methodologies, together with the benefits to PCB manufacturers, end users and test laboratories.

Jan Pedersen, director of technology for NCAB Group in Norway, examined the dividing line between ultra-HDI PCBs and IC substrates, and reviewed related standards and capabilities. 

Pedersen defined ultra HDI PCB, which is referred to as products with lines and spaces below 50 microns, dielectric thicknesses below 50 microns, microvia diameters below 75 microns, and product attributes beyond the existing IPC-2226 Level C. With the aid of a schematic representation of chips sitting on redistribution layers, in turn sitting on interposers with through-silicon vias, in turn sitting on a package substrate, finally sitting on a PCB, with the assembly joined up mechanically and electrically by solder bumps and balls, he demonstrated the basics of heterogeneous integration—combining PCB, IC substrate and chip as an example of the use of advanced packaging technology to integrate devices which could be separately designed and manufactured by the most suitable process technology. 

Pedersen commented that standards are in development for UHDI with attributes beyond current IPC-2226 Level C limits. He believes that established subtractive manufacturing processes might reach 40 micron lines and spaces, but anything finer will require changing to a semi-additive technology. The capability limit for ultra-fine-line manufacture is effectively determined by the base copper thickness, and whereas traditional subtractive processes normally required base foils of 12 microns or more, current semi-additive processes could start as low as one micron of electroless copper.

Speaking as co-chair of the IPC D-33AP task group for ultra HDI PCBs, Pedersen described a draft for implementing UHDI to IPC-2226 Table 5-1 and three suggested UHDI classifications, representing a typical advanced subtractive etch process, a typical advanced mSAP process and a typical SAP process. 

He next discussed some aspects of the EU Chips Act and how it compares with its U.S. counterpart, before focusing on market projections for UHDI and its availability. A new market is growing, and PCB manufacturers will need to extend their capability if they are to benefit from the opportunity. Investment in super-clean imaging areas are be a primary consideration.

He finished his presentation with some very helpful guidelines and notes on applications, materials and design rules.

Pedersen’s mention of design rules and guidelines provided a link to the third presentation. Peter Tranitz, senior director, technology solutions at IPC Europe, introduced new ways to approach electronic design with a “silicon-to-systems” strategy for enabling electronic design for excellence. 

Tranitz cited a white paper shortly to be issued by the IPC Design Leadership and Chief Technologist councils, entitled “Next Generation Design Needs,” which recognises that electronic systems are increasingly complex and heterogeneous. The principal message delivered by the white paper is that a silicon-to-systems design ecosystem requires flawless collaboration and interoperability between subdisciplines and systems. It states that facilitation of an Authoritative Source of Truth (ASOT) is mandatory to ensure consistency, efficiency, and traceability, and further advises that diverse electronic and mechanical CAD systems must gain interoperability by including proper model-based definitions and collaborative software to cover both disciplines. The white paper defines design rules as a set of parameters to ensure an accurate design, and advises that compliance with design rules should be checked throughout the entire design process.

Regarding design for manufacture, it makes it clear that DFM analysis at handover from development to manufacturing flags design flaws is too late and increases cost. A shift in paradigm toward true digital collaboration and automation, and an early consideration of manufacturing capabilities throughout the entire development process, is essential.

Tranitz reviewed IPC’s design offerings: standards, education, events, and new solutions. He listed the IPC design standards under major revision and those new design standards under construction, including the IPC-2229 design standard for UHDI, which Jan Pedersen had mentioned. He also discussed verifying designs to IPC standards to ensure manufacturability, implementing IPC DFM profiles, and using the web-based PCBflow platform for DFM analysis.

The three technical speakers were joined by Alison James, senior director, IPC Europe, for a panel Q&A session, moderated by Rapala-Virtanen. They responded to questions from the audience on microvia reliability, UHDI availability and manufacturability in Europe, and UHDI manufacturing processes.

James was asked her opinion of the government’s understanding of the realities of the state of the European electronics industry, its future, and the limitations of the EU Chips Act. She said IPC is making sure that governments at the European and national levels understand the significance of electronics manufacturing and the critical importance of printed circuit boards. Progress is being made. Morgan once more implored members of the audience representing companies and organisations to please sign and support EIPC’s Letter of Urgency. 

I was amused to observe how the roving microphone has progressed from a stick-on-the-end-of-a-wire to a cordless soft cube that can literally be thrown around the room from person to person. Very effective, and good netball practice.

Continue reading the second part of this series, Looking Into Space: EIPC Summer Conference, Part Two

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