Dan’s Biz Bookshelf: 'This Is Strategy: Make Better Plans'
The Chemical Connection: Reducing Defects in Circuit Board Production
It’s Only Common Sense: Trust Is All You Need
Dream Chip, Cadence Demo Automotive SoC Featuring Tensilica AI IP at embedded world 2024
June 19, 2024 | Cadence Design Systems, Inc.Estimated reading time: 2 minutes
At embedded world 2024, Cadence and Dream Chip demonstrated Dream Chip’s latest automotive SoC, which features the Cadence® Tensilica® Vision P6 DSP IP and Cadence design IP controllers and was taped out using the complete Cadence® Verification solution and full-flow digital implementation, including signoff. The advanced driver-assistance system (ADAS) application software, operating on the Tensilica AI IP within the Dream Chip development board, was a highlight of Cadence's booth during the exhibition held in Nuremberg, Germany, from April 9 to 11.
This innovative SoC utilizes the GlobalFoundries 22FDX® technology platform, which is ready and proven for energy-efficient automotive customers. The SoC is designed in a publicly funded project, ZuSE-KI-Mobil (ZuKIMo). ZuKIMo focuses on developing an AI accelerator system on chip (SoC) for advanced driver assistance systems (ADAS). Manufactured in Dresden, Germany, the SoC supports the local European semiconductor supply chain for automotive applications.
The Cadence Verification, Implementation and Signoff solutions enable automotive designers to quickly deliver first-time silicon success while achieving safety, quality and reliability goals, enabling certification up to ISO 26262 ASIL-D, with minimal impact on system power, performance and area (PPA) targets. This cutting-edge SoC leverages the capabilities of Cadence verification and RTL-to-GDS digital full-flow solutions, meticulously fine-tuned to meet the stringent safety, quality and reliability standards required in the automotive industry.
It also leverages the optimal ADAS features with the industry-leading Tensilica Vision P6 DSP and AI cores by incorporating Tensilica AI processors and a sophisticated array of Digital IP controllers. These include Cadence’s pioneering NPU AI IP, multi-functional Ethernet 10/100/1G MAC, essential control features such as SPI and RTC Control, and SD 6.0/eMMC 5.1 Host Controller and PHY. This strategic integration of hardware is designed to power energy-efficient ADAS applications that utilize evolving technologies like lidar, radar and vision-based systems at the edge, significantly enhancing the automotive-grade quality, safety and reliability of autonomous, connected and electrified (ACE) vehicles.
Commenting on the milestone, Dr. Jens Benndorf, managing director and CEO of Dream Chip Technologies, said, “We collaborated closely with Cadence to provide a full automotive solution highlighting Cadence Tensilica AI-at-the-edge performance along with functional safety and the latest image signal processing to automotive OEMs and Tier-1s. Dream Chip fully implemented and signed-off the energy-efficient automotive SoC from architecture spec to running software using the Cadence Verification solution along with the Cadence Digital EDA full-flow on the GlobalFoundries 22FDX process, showing that Dream Chip is an optimal design house choice for advanced automotive SoCs.”
David Glasco, VP of research and development, Compute Solutions Group at Cadence, added, “The choice of Tensilica IP by the ZuKIMo coalition along with Cadence’s focus on design innovation and excellence across all aspects of the safety-critical and high-reliability IP and the design and verification flow has resulted in this powerful ADAS demo.”
The embedded world demo highlighted the advanced SoC capabilities, demonstrating the power and flexibility of Cadence’s Tensilica IP in driving optimal ADAS features with the industry-leading Vision and AI cores.
Share on:
Suggested Items
Cadence Extends Support for Automotive Solutions on Arm Zena Compute Subsystems
06/05/2025 | Cadence Design Systems, Inc.Cadence announced IP, design solution, and expert design services for software and Systems-on-Chip (SoCs) based on Arm® Zena™ Compute Subsystems (CSS), Arm’s first-generation CSS for automotive.
Cadence, AVCC to Advance Physical AI Innovations for Autonomous Vehicles
05/12/2025 | Cadence Design SystemsCadence has joined the Autonomous Vehicle Computing Consortium (AVCC), marking a significant step forward in Cadence's commitment to advancing autonomous vehicle technology for the physical AI era by working with industry leaders to define high-performance computing (HPC) and safety solutions for next-generation autonomous vehicle systems.
Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
05/01/2025 | Cadence Design SystemsCadence announced a significant expansion of its portfolio of design IP optimized for Intel 18A and Intel 18A-P technologies and certification of Cadence® digital and analog/custom design solutions for the latest Intel 18A process design kit (PDK).
Cadence Reports Q1 2025 Financial Results
04/29/2025 | Cadence Design SystemsQuarter-end backlog was $6.4 billion and current remaining performance obligations ("cRPO"), contract revenue expected to be recognized as revenue in the next 12 months, was $3.2 billion
Cadence Enables Next-Gen AI and HPC Systems with Industry’s Fastest HBM4 12.8Gbps IP Memory System Solution
04/21/2025 | Cadence Design SystemsCadence announced the industry’s fastest HBM4 12.8Gbps memory IP solution, which meets the increasingly higher memory bandwidth needs of SoCs targeted for the next generation of AI training and HPC hardware systems.