Estimated reading time: 11 minutes

Happy’s Tech Talk #31: Novel Ultra HDI Architectures

Ultra HDI has become the focus for many fabricators, especially as the follow-on for the 40-year-old conventional HDI. But there is more to UHDI than just finer traces and spaces. Novel architectures have been developed that complement the new dense lithography. Figure 1 shows four of them:

1. Swing blind microvias¹
2. Vertical conductive structures (VeCS)²
3. Integrated mesh power systems³
4. Power mesh⁴

One of the major advantages of HDI, and especially ultra HDI, is the miniature features of the process. Since the microvias and lands are so small, they can be swung around at various angles between the BGA lands, as seen in Figure 2. The angles and distances (Table 1: E, G) will depend on the BGA pitch (Table 1: A) and where the microvia is placed relative to the BGA SMT land (Figure 3).

HDI Stackups
Chapter 3 of the HDI Handbook1 shows multiple stackups that provide for distributed capacitance and X-Y routing layer pairs (Figure 4). The finer geometries of UHDI and HDI require thinner dielectrics to maintain their impedances, which can also lower cross-talk and improve signal integrity and PDN impedances.

Boulevard Routings
The biggest gains from these HDI structures are the additional routings available on inner layers (Figure 5). By concentrating the BGA breakout microvias together, many additional routing channels are opened up. This allows many more traces for the breakout that could not be achieved with the conventional N-S-E-W dog-bone breakout structure and with only two laminations. This is coupled with the ground plane moved to the surface for improved return paths. Complex and high-density BGA can be connected with very few build-up layers, increasing reliability and ease of construction (Figure 6).

Vertical Conductive Structures (VeCS)
VeCS was developed by NextGIn Technologies from the Netherlands in 2017. The innovative, true 3D structure provides for vertical layer connections to layers without sequential lamination by using routed trenches. The trenches are made during drilling with new, special drill/router bits produced at various controlled depths. The trenches allow metallization and plating, as seen in Figures 1 and 7a. 

As an example, my TechTalk #12 provides an example of a 4+4+4 (Figure 7b) HDI build-up replaced by the VeCS example in Figure 7c with only one lamination and no laser-drilled microvias or in Figure 7d with the use of microvias over the VeCS core.

VeCS is used for interconnections by creating a routing channel (slot) in the printed circuit that then can be metallized and plated easier than high-aspect ratio vias and will allow connection to inner layers. The channels can be created by existing PCB fabrication equipment. This allows HDI densities without significant added costs yet easier fabrication processes and higher electrical performance and reliability. The process and applications already developed by NextGIn Technologies are: VeCS-1, -2, and -HDI. The three main combinations of their interconnect slot technology:

• VeCS-1: Where the channel (slot) goes through the substrate
• VeCS-2: Where the slot is formed as blind or in a hybrid-blind and through-slot combination
• VeCS-HDI: Laser-drilled microvias are used for fine-pitch utility on ultra-fine-pitch components

With channels (slots) formed from both sides, the 3D vertical traces provide greatly increased density without sequential laminations. Replacing larger through-hole with slots provides better power integrity for new power-hungry chips while lowering inductance and capacitance for improved signal integrity.

The Channel or Slot
The all-important step of metallizing and plating the typical 0.3-mm blind slot (Figure 7a) is shown in the column of various depths and lengths (from depths of 0.47 mm to 1.23 mm and lengths of 0.6 mm to 1.8 mm). Some of the smaller aspect ratios have insufficient chemical exchange but the majority have excellent chemical exchange for normal plating baths. The new alternative drill/router bits have successfully created channels of 0.1 mm with straight walls and no burring. 

Fabrication Process
The VeCS fab process starts with a conventional through-hole multilayer. The process has eight steps:

1. Create slot
2. Plate slot
3. Alignment in BGA pin field
4. Resin fill PR slot and PR stencil
5. Drill CR slots
6. If vertical traces are used, drill BR slots
7. BR/CR stencil
8. Resin fill BR/CR slot

First, after drilled vias are completed, the primary cross-rout (CR) slots are put in. Here, a special drill/router bit uniquely suited for this operation is used. Much work and experimentation were conducted to perfect an ideal drill/router bit for this task. Then metallization and copper plating are performed. Resin is now used to fill the CR slots. Curing is the important step of cross-routs that create the vertical interconnects. If vertical traces are used, drill/rout out the back-rout (BR) slots. Then, selected vias and slots are resin-filled and cured. In step 7, for pattern plating, the normal process resumes of imaging, plating, stripping, and final etching. In the final panel, the board would be solder masked, with any final finishes and fabrication.

Figure 7e shows a 3D cut plane view and the inner layer connection and surface connection views for VeCS.

Integrated Mesh Power Systems (IMPS)
In the late 1990s, thin-film multichip modules (MCM-D) were to be the salvation of the interconnect industry. Fine-line lithography would allow miniaturization with ease. Unfortunately, the four or five metal layers to which integrated circuits were wire-bonded proved to be too expensive compared to printed circuit multilayers and the emerging silicon integration on ball grid arrays.

IMPS technology was created to reduce the cost and metal layers on thin-film and ceramic multichip modules. The IMPS topology can reduce the metal layers to only two or three. This results in a substantial cost reduction and simplification while not affecting electrical performance.

Background: IMPS
The scientists at the High-Density Electronics Center (HiDEC) of the University of Arkansas, Fayettville, invented IMPS in the mid-1990s. IMPS allows a low inductance co-planar power and ground distribution, as well as dense, controlled-impedance, low crosstalk signal transmission in only two wiring layers. Figure 1³ shows the basic IMPS technology.

The conventional metal wiring topology is to have signals on one metal layer and power and ground on separate metal layers. The resulting usage of these expensive metal layers is quite low. Signal layers may have only 50–60% utilization and power/ground layers only half that amount when either the coarse mesh or fine mesh is utilized.

They may be made smaller (if signal losses can be tolerated), but the spacing cannot. High-speed, fast rise-time signals are sensitive to crosstalk, so the signals still must be separated. IMPS uses that separation to route power and ground. To prevent current starvation at devices, an adjacent metal layer running orthogonal is connected by buried vias at each junction where the two layers cross each other. This layer-pair topology is an “interconnected mesh” that can thus provide all the power/ground connections without voltage loss and connect the signal for these devices.

IMPS Design
IMPS was developed in the late 1990s for MCM-D design using thin-film metallization on liquid dielectrics. Fortunately, PCB technologies have improved in the last 30 years such that UHDI technologies can now achieve these thin-film geometries. The various SAP metallization on polyimide film or ABF organic films can be employed, including the use of metal-backed thermal laminate.

The architecture is based on the current use of a power mesh in integrated circuit design. But instead of the single metal use, IMPS employs two metals and adjacent layers, connected by vias, to form the mesh (Figure 8). In Figure 8a, L1 and L2 are the ground mesh, while Figure 8b, L1: VCC-L2: VCC and L1: VDD-L2: VDD shows the power mesh. The two are merged with the open area of X-Y routings, as seen in Figure 8c as L1: signal–L2: signal.

High-density MCM-BGA Application
In 1996, HiDEC used flexible film and tape BGA (TBGA) technology along with microvias and the IMPS topology, to create an MCM-L with only two metal layers instead of the conventional four metal layers of an MCM-D. This test vehicle puts two IMPS metal layers, which provide signal wiring and power distribution, on the two sides of a polyimide film. One side contains mounting pads to which the dies are wire bonded and discretes are soldered. This side is encapsulated. The other side has the lands in a ball grid array pattern. A part of the IMPS artwork is shown in Figure 8.

The test vehicle was built on 2-mil Sheldahl adhesiveless polyimide film, ViaThin™. The basic design rules are 50 µm lines and spaces, 150 µm via target lands over 25 µm laser drilled vias. The IMPS mesh consisted of 200 µm lines and 50 µm spaces, with the lines offset from the via row or column centers. Wirebond pads consisted of 200 µm  x 350 µm rectangles on both metal layers, tied together with two vias.

Power Mesh Architecture (PMA)
The power mesh architecture was derived from the interconnected mesh power system (IMPS) developed and patented by HiDEC⁵. The IMPS topology was created to reduce the cost and metal layers on thin-film and ceramic multichip modules.

The power mesh architecture (PMA) for PCBs is presented in Figure 9. My Tech Talk on PMA⁵ has impedance tables as well. The initial application of PMA is shown, as well as an application that helps develop the wiring density model for PMA.

In 1993, a large electronics OEM had the problem of having to redesign the control board of their largest 3.5" hard disk drive. The boards were a standard 3.87" x 5.45" but their problem was that they wanted to cut a 2.8" diameter hole in the board so that another platter could be added to the drive. This would enable the drive to have a capacity of 16 GB, quite a capacity for 1993. The solution to the loss of nearly 5.8 square inches out of 17.5 square inches was to employ microvias and microvia-in-pads. The new microvia board (called Lynx) was designed with a reduced surface area and as a six-layer design (1+4+1), two fewer layers than the original.

Reading about the IMPS topology from HiDEC in 1994, the Lynx board was again redesigned to a four-layer construction. To minimize the microvias, the outer two layers (1 and 4) were flooded with ground and only power and signals were placed on the inner layers. Figure 1⁴ shows the new power-signal routing architecture, which was called power mesh to differentiate it from IMPS.

Electrical Model
The original Lynx board was not controlled impedance, but additional PCB designs that used power mesh were. The consensus is that power mesh is an offset coplanar stripline. Figure 9 shows the cross-section and stack-up for the PMA.

The crosstalk model indicates that the power mesh architecture creates a naturally low crosstalk condition. Each signal trace of X-width is approximately 3X or 4X distance from the next signal, depending on the power trace width. This creates horizontal crosstalk of less than 2%. The vertical crosstalk is extremely low. From 15 mV/V for thin cores (0.012") to 2.6 mV/V for a thick core (0.051").

Wiring Model
In 1994, StorageTek, an OEM in Colorado, conducted performance benchmarking with microvia designs and fabrication. The successes of that program contributed to its continued use of microvias. In 1998, it became apparent that they required some wiring model to indicate that a microvia structure was required. In performing that model development, a power mesh benchmark was designed for one of the microvia boards. Figure 5 in Tech Talk #28 shows the two inner layers of the four-layer power mesh structure and two of the six inner layers from the original eight-layer through-hole design. The wiring density model for the power mesh architecture is:

Power mesh = 17 to 40 signal inches per square inch per layer*

• Calculate the statistical wiring density using Coors, Anderson & Seward⁴
• Calculate the Manhattan wiring density using Wd=0.0068(X)^2 – 0.1644(X) + 35.1, where X is the Coors statistical wiring density.
• Calculate the routability index for power mesh
• Calculate the layout efficiency using L.E. (%)= 4.0642(RI)^-1.189, where RI is the routability index

                                      *  dependent on trace width and spacings

Summary
The new microvia topologies of swing vias, VeCS, IMPS, and power mesh have demonstrated that applications to simplifying complex multilayer, PBGAs, and MCMs to UHDI are available. VeCS can reduce process costs; IMPS can reduce the structure to a two-metal interconnect, while power mesh uses a four-layer, reinforced laminate structure. These results show that these topologies have the capacity of positively impacting how electronic products are packaged and interconnected.

References

1.  Chapter 3: Swing Vias, The HDI Handbook, by Happy Holden, I-Connect007.
2.  Happy’s Tech Talk #1: Vertical Conductive Structures (VeCS), by Happy Holden, PCB007 Magazine, October. 2021.
3.  I have written nine articles on VeCS for PBC007 Magazine.
4.  Happy’s TechTalk #27: Integrated Mesh Power System (IMPS) for PCBs, by Happy Holden, PCB007 Magazine, March 2024.
5. Happy’s Tech Talk #28: The Power Mesh Architecture for PCBs,” by Happy Holden, PCB007 Magazine, April 2024.

Happy Holden has worked in printed circuit technology since 1970 with Hewlett-Packard, NanYa Westwood, Merix, Foxconn, and Gentex. He is currently a contributing technical editor with I-Connect007, and the author of Automation and Advanced Procedures in PCB Fabrication, and 24 Essential Skills for Engineers. 

This column originally appeared in the July 2024 issue of PCB007 Magazine.