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Avnet Announces Release of Autodesk Fusion Integration
October 16, 2024 | AvnetEstimated reading time: Less than a minute

Design engineers can now access thousands of reference design schematics, lead time and pricing trends, and fast alternate guidance with the launch of the Avnet App, an add-in for Autodesk Fusion.
Avnet is the first to add these design capabilities and insights via a globally available add-in to the Autodesk Fusion solution. The Avnet App will give design engineers access to a powerful part search, alternates library, project cost and supply chain health analysis, datasheets, component symbols and more.
Autodesk Fusion is a cloud-based 3D modeling, CAD, CAM, PCB and mechanical engineering solution for product design and manufacturing. Avnet’s new features are offered as a Fusion add-in to streamline design workflow, helping design engineers meet functional requirements, cost targets, manufacturing goals, and lifecycle timelines.
“As a key technology partner in the early stages of design and product realization, Avnet provides engineers with valuable tools through the app,” said Chris Jackson, VP, Digital Strategy and Innovation, Avnet. “The reference design library is full of schematics and project descriptions that engineers can directly place into their designs with a simple in-app search in as few as three clicks.”
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Bridging the Gap Between PCB Designers and Fabricators
04/03/2025 | Stephen V. Chavez, Siemens EDAWith today’s advanced EDA tools, designing complex PCBs in the virtual world does not necessarily mean they can be built in the real world. This makes the relationship between a PCB designer and a fabricator pivotal to the success of a project. In keeping with solid design for manufacturing (DFM) practices, clear and frequent communication is needed to dial and lock in design constraints that meet expectations while addressing manufacturing concerns.
IPC APEX EXPO Newcomer: Faith DeSaulnier of TTM Technologies
04/03/2025 | I-Connect007 Editorial TeamDuring the Newcomer’s Welcome Reception at IPC APEX EXPO, the I-Connect Editorial Team spoke with several first-time attendees. The following is our interview with Faith DeSaulnier, a process engineer based at TTM Technologies’ facility in Forest Grove, Oregon.
Ansys Semiconductor Solutions Certified by TSMC for Reliable, Accurate Analysis of Evolving Chip Designs
04/03/2025 | PRNewswireAnsys announced that PathFinder-SC is certified as a new ESD analysis solution for customers designing with TSMC's N2 silicon process technology. PathFinder-SC delivers a novel verification solution that provides superior capacity and performance, easily accommodating large designs in the cloud.
Real Time with... IPC APEX EXPO 2025: Insights into PCB Design and Manufacturing with Polar Instruments
04/03/2025 | Real Time with...IPC APEX EXPOErik Bateham discusses Polar's latest book, which enhances insights for PCB designers and manufacturers. The book, "The Designer's Guide to... More Secrets of High-Speed PCBs," features a guest chapter on 2D via design modeling. Erik highlights the industry's shift towards UHDI and the challenges in measuring at micron levels.
Connect the Dots: Stop Killing Your Yield—The Hidden Cost of Design Oversights
04/03/2025 | Matt Stevenson -- Column: Connect the DotsI’ve been in this industry long enough to recognize red flags in PCB designs. When designers send over PCBs that look great on the computer screen but have hidden flaws, it can lead to manufacturing problems. I have seen this happen too often: manufacturing delays, yield losses, and designers asking, “Why didn’t anyone tell me sooner?” Here’s the thing: Minor design improvements can greatly impact manufacturing yield, and design oversights can lead to expensive bottlenecks. Here’s how to find the hidden flaws in a design and avoid disaster.