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Keysight, Synopsys Deliver an AI-Powered RF Design Migration Flow
June 6, 2025 | BUSINESS WIREEstimated reading time: 2 minutes
Keysight Technologies, Inc. and Synopsys, Inc. introduced an AI-powered RF design migration flow to expedite migration from TSMC’s N6RF+ process to N4P technology, to address the performance requirements of today’s most demanding wireless integrated circuit applications. Building on TSMC’s Analog Design Migration (ADM) methodology, the new RF design migration workflow integrates RF solutions from Keysight and the AI-powered RF migration solution from Synopsys to streamline the redesign of passive devices and design components to TSMC’s more advanced RF process rules.
RF circuit designers can now use AI technologies for RF design migration with TSMC’s ADM methodology. Beyond the productivity gains offered by ADM, the Keysight and Synopsys migration workflow leverages the performance gain of the N4P process for the LNA design migrated from N6RF+. Key components of the design migration flow include the Synopsys Custom Compiler™ layout environment with Synopsys ASO.ai™ for rapid analog and RF design migration, Synopsys PrimeSim™ circuit simulator, and Keysight RFPro for device parameterization, automated value fitting, and electromagnetic (EM) simulation.
AI enables and aids RF circuit designers in a novel way to rapidly achieve the migration process and redesign to the N4P process, resulting in faster time-to-market. Synopsys Custom Compiler, along with ASO.ai, an AI-driven analog design migration solution, identifies optimal design parameters to meet performance metrics. Keysight RFPro enables parameterization of passive devices, including inductors, and automatically re-creates simulation models with layouts tuned to the new process rules.
Sanjay Bali, Senior Vice President of Strategy and Product Management at Synopsys, said: “Analog design migration is a challenging and time-intensive process requiring significant trial and error. Our deep collaboration with Keysight Technologies and TSMC enables design teams to boost their productivity with an AI-powered RF design migration flow to accelerate the redesign process and deliver RF designs more efficiently, while achieving the best PPA (Power, Performance, and Area) on TSMC’s advanced nodes.”
Niels Faché, Senior Vice President of Keysight’s Design Engineering Software, said: “Meeting PPA requirements while adhering to new process design rules is one of the biggest challenges facing complex RF chip designs. RF circuit designers want to leverage and reuse their libraries of N6RF+ devices and component intellectual property to improve ROI. The deployment of Synopsys ASO.ai for efficient analog design migration and Keysight RFPro for passive device modeling within TSMC’s ADM methodology facilitates accelerated redesign in the advanced TSMC N4P technology for existing components originally built in N6RF+. No time-consuming data handoffs or domain specialization are required, which increases overall engineering productivity for RF circuit designers.”
Lipen Yuan, Senior Director of Advanced Technology Business Development at TSMC said: “We offer a powerful combination of advanced logic and mixed signal/radio frequency (MS/RF) technologies, enabling our customers to design differentiated wireless connectivity products. Through collaboration with our Open Innovation Platform® (OIP) design ecosystem partners such as Keysight and Synopsys, we’re delighted to deliver a highly efficient RF design migration flow. This enables our customers to quickly transition their designs to more advanced processes, maximizing performance and power efficiency benefits while accelerating time-to-market.”
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A Designer's Focus on High Density
04/30/2026 | Marcy LaRont, I-Connect007 MagazineVern Solberg is a distinguished member of the Global Electronics Association Raymond E. Pritchard Hall of Fame and has served as chair or vice chair of many committees, developing technical standards and implementation guidelines, including the IPC-7090 series, which focuses on design for manufacturing and reliability for electronic assemblies. He’s a long-time contributor to Design007 Magazine, and he conducted a half-day tutorial at APEX EXPO 2026, where he addressed 2D, 2.5D, and 3D packaging and ultra-high density hybrid bond interconnect. I caught up with Vern at the show and asked about his pivot from addressing more standard design challenges to his focus on high-density circuits.
Zuken Launches GENESYS 2026 to Broaden Access and Improve MBSE Workflows
04/28/2026 | ZukenZuken announced GENESYS 2026, the latest version of its model-based systems engineering platform, with updates designed to improve performance, expand access to model-based information, and enhance the day-to-day modeling experience for engineering teams.
EDADOC: Building the ‘Neural Hub’ for High-Compute Chips Within a Compact Space
04/28/2026 | ECIOEvery chip to the market must pass a stringent checkpoint before shipment known as ATE testing. Serving as the physical “neural hub” that connects test equipment worth millions of dollars with the device under test, the performance of the ATE test board directly determines the accuracy, efficiency, and final yield of chip testing. Amid the rapid rise of high-compute chips, what extreme challenges is this seemingly small circuit board facing? How is EDADOC addressing industry pain points through its one-stop “design + manufacturing” model?
Cadence Reports Q1 2026 Financial Results
04/28/2026 | Cadence Design SystemsCadence had a strong start to 2026, delivering a solid Q1 with accelerating AI demand and record backlog, reflecting strong customer commitment to our AI-driven portfolio,” said Anirudh Devgan, president and chief executive officer.
Tomachie Launches AI-Powered PCB Analysis with Smart Test Point Insertion
04/28/2026 | TomachieTomachie announced its AI-Assisted PCB schematic design analysis platform, enabling engineering teams to evaluate and improve schematic quality before layout begins. Schematic errors caught after layout — or in production — cost 10 to 100 times more to fix than those caught during schematic capture.