Advanced Packaging: Preparation is Now

Estimated reading time: 9 minutes

In this interview, Matt Kelly, CTO for the Global Electronics Association, and Devan Iyer, chief strategist of advanced packaging, define advanced electronics packaging and the critical nature of getting it right in the electronics manufacturing field.

They share details from their white paper, “Advanced Packaging to Board Level Integration—Needs and Challenges,” and provide insight into how next-generation packaging will change the design, fabrication, and assembly of printed circuit boards, including the implications for final system assembly.

Nolan Johnson: Your white paper on advanced packaging is a very technically deep, insightful piece with great detail. What's the ultimate goal?

Matt Kelly: Our intent was to go one layer deeper into our silicon-to-systems messaging. You've heard this phrase as a way to describe what's happening at the front end of the supply chain, from chips to the final system. The report begins by talking about applications. It's important to understand that advanced packaging is very broad, so we break down what it means to drive market segments.

For example, advanced packaging means different things in different applications, such as high-performance computing (HPC), 5G/6G wireless communications, autonomous driving and EV automotive, medical electronics, and aerospace and defense systems. Depending on the type of environment and product you're dealing with, the challenges, needs, and requirements for what these advanced packaging techniques can deliver will vary.

This report is important because it combines two concepts—component-level packaging (CLP) and system-level packaging (SLP)—which are obviously related.

It’s important to convey that the amount of time, effort, and investment IPC has made to stay on top of changes with advanced packaging will be ongoing and is here to stay. A long time ago, someone taught me that “everything follows silicon”; just watch what it does, and everything else will follow. That lesson holds true here, too. People are already doing a lot of this work. Products and devices are using this technology as we speak. This is not “someday”; it's actually happening now. But as with everything else, there's breadth to this for the entities unaware of these challenges. We know it’s important for our membership and the industry that we stay on top of this.

Most importantly, we're not just reporting information but rather giving it a subject matter expert assessment by discussing and analyzing it. What are the impacts for a designer, PCB fabricator, assembler, or manufacturer making new components?

It's important that we identify and digest this and give recommendations and key highlights of what's happening. You've heard me say many times that a component by itself, while it's really amazing, doesn't do anything until it's attached to a larger circuit system and board.

Johnson: Devan, the report clearly shows that component-level (CLP) and system-level (SLP) packaging receive a lot of attention.

Devan Iyer: That's right. With CLP, there is a lot of integration happening that includes single-chip and multi-chip heterogeneous integration.

Multi-chip heterogeneous integration brings different silicon technology nodes integrated into one package. Different material sets, silicon, and non-silicon devices can be integrated into one package or module in a heterogeneous integration technology.

Those heterogeneous integrations happen inside a CLP. The challenges associated with integrating CLP into a board are multifold. You need to really look at the design elements. How do you design the PCB to cater to the requirements of a complicated CLP—a heterogeneous integrated package?

What material sets must be used to integrate those packages into the board? What type of solders and interface materials do you need? As CLPs become increasingly complicated, these questions need to be extensively studied.

The next point we address is to be very mindful of the assembly processes, which are the PCB assembly processes typically used in the EMS world. How will these packages be socketed? How will they be integrated with sockets and/or without sockets?

Finally, we address the reliability and characterization of these complex packages as we integrate them into the board or as we assemble them. In addition to the application space and the differentiation of packaging for the application space that Matt mentioned earlier, we also need to look at each of the elements of design, materials, assembly, reliability, and metrology. Those are highlighted in this paper.

Johnson: Devan, will you discuss the difference between CLP and SLP?

Iyer: CLP comes in when a device needs to be packaged. The industry does this in two different ways: a single-chip package and a multi-chip module. Within CLP, one chip can be attached to a single package. That’s a single-chip package (SCP). When multiple devices are integrated into a package, that becomes a multi-chip module (MCM).

For heterogeneous integration, that multi-chip module can have a silicon chip and a nonsilicon chip, such as a silicon-based chip and a gallium-nitride chip or maybe a silicon chip and silicon carbide chip. Today, they all come in different flavors. The multi-chip modules and the substrate that we use inside can be silicon substrates, ceramic or laminate substrates, or glass substrates. The industry is also bringing glass substrates these days.

Now, SLP starts once the chips are integrated into a single-chip or multi-chip package; they must then be assembled to the board. That's where the system-level packaging starts. It goes from package to board and then board to racks to final system assembly (FSA). Some people interpret CLP and SLP as first-level and second-level packaging. When you look at the textbooks, some refer to the component-level packaging as first-level packaging, and system-level packaging as second-level packaging.

Johnson: You really detail those in your report and discuss the challenges and opportunities for optical.

Iyer: Yes. As we go in for higher-speed interconnects, we talk about packaging for high-speed applications, but packaging and interconnects need to be thought through as one entity. There are no packages without interconnects, whether they are traditional wire bond interconnects or flip-chip interconnects. Optical interconnects are finding their way to very high-speed interconnections as an alternative to traditional copper-based interconnects. We need the bandwidth and lower latency for high-performance computing and very high data communication rates. These demands are pushing into optical-based interconnects. The term we commonly use is co-packaged optics (CPO), where the optical component and electronic components are integrated into one package.

Johnson: This has implications down the road for what EMS companies will need to assemble.

Iyer: Absolutely. For assembling optical components into the board, you are dealing with fiber-based optical interconnects, so how do you assemble them efficiently? You're coupling light; it's not coupling electrical signals there. How do you keep the coupling efficiency high during assembly? That is the key challenge that must be addressed between the packaging and board assembly communities.

Johnson: You have been spearheading extensive research on advanced packaging recently. What are you looking to accomplish for the electronics industry with this work?

Kelly: It's a multifaceted answer. The Global Electronics Association spends a lot of time on advocacy, working on behalf of our members to be the voice of the electronics industry to governments. As Devan mentioned earlier, we work globally and regionally, and the work we've done over the past several years with advanced packaging started at that highest level of advocacy. We’ve addressed questions like, “What is needed? Where are there gaps? Where can investments be made? How can we help governments and companies in certain regions bolster their capabilities?”

Over time, certain things in the supply chain can, will, and have moved. But make no mistake, the global supply chain is alive and well, and for a sustainable business, different geographies will be the primary supply base of certain electronics elements.

This portfolio of reports started with advocacy, but we're going deeper into the actual subject matter, answering questions like: “What types of technical challenges are there? What do companies need and want to be standardized in their factories and trained with their workforce?” We've been working at the highest levels within various governments, including the U.S. government, the European Parliament, and Asian governments, including Japan and others.

You'll also notice that we write on topics that are top of mind in the industry. We’re always writing about the latest needs and wants, giving our members as much insight as possible.

Iyer: IPC member companies typically consist of OEMs, EMS suppliers, and PCB fabs. Meanwhile, component-level packaging is primarily done by OSATs and IDMs. That places system-level packaging with the OEMs, EMS suppliers, and PCB designers and manufacturers. This white paper addresses the challenges for component-level packaging as they integrate into system-level packages. In other words, we are trying to connect the CLP and SLP.

What trends does the component-level packaging community bring to the system-level packaging space? This white paper acts as a prelude to assessing the industry interests as well.

Johnson: The OEMs own the big-picture view here. Their perspective and intellectual property are what connect the silicon to systems.

Iyer: OEMs own connecting the dots all the way from device to package, from single-chip package to multi-chip package to a board to the system assembly. As chip technology moved quickly, component-level packaging technology lagged behind. That gap is getting closed now. Now, system-level packaging also needs to close the gaps. The question is how do we close the gap between component- and system-level packaging?

Johnson: Your team is not exactly resting on its laurels after this report. You've already gone to another level of detail with a subsequent report published recently.

Kelly: Right. The follow-up report, which was released in early October, is on AI-based data centers in the United States. This is an example of a regional report and a study that Devan, Chris Mitchell, and I worked on. It has many of the same elements in terms of flow. Devan has been with us for less than a year and has already helped us tremendously. We're building IPC’s expertise in silicon-to-systems technology capability. As we do that, we continue to produce meaningful and valuable research, white papers, and industry intelligence reports.

Johnson: Matt and Devan, why does all this matter?

Kelly: We are at the beginning of a 10-plus-year disruptive change. If you are a component maker somewhere in that supply chain, you're already seeing these changes. Silicon is being stitched in different ways: You have to put it on different substrates and package it differently; we're stacking everything. If you're in the component-level packaging realm, you're seeing the impacts of this disruptive change. Now, if you're more on the PCB fabrication, printed circuit board assembly, or final system-level packaging side, you may not see this yet, but it is coming fast—and it matters.

Johnson: Thank you.