Siemens Accelerates Complex Semiconductor Design and Test with Tessent IJTAG Pro

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Siemens Digital Industries Software announced Tessent™ IJTAG Pro software, which will transform IJTAG (IEEE 1687) input/output by enabling parallel operations of the traditionally serial operation and provide read and write access to custom hardware. The new software introduces high-bandwidth internal JTAG (IJTAG) and generic data streaming functionality to help customers reduce test cost and time by accelerating data using the wide bus of Siemens’ Tessent Streaming Scan Network (SSN) software.

The semiconductor industry is facing an unprecedented and accelerated evolution as transistor density expands across multiple dimensions. As semiconductor designs advance from 2D to 2.5D to full 3D IC architectures, design testing challenges have multiplied exponentially. The escalating test pattern counts, longer pattern application times, high ATE (Automatic Test Equipment) costs and limited number of test pins accessibility mean that optimizing existing infrastructure for test scaling is not just crucial but imperative for maintaining a competitive edge in the design process.

“In today’s complex IC designs, test time optimization is a significant challenge. By utilizing Siemens’ SSN architecture to convert traditional serial IJTAG operations into high-bandwidth parallel processes, Tessent IJTAG Pro not only accelerates test and reduces cost associated with test but also provides flexibility needed for revolutionizing test access to meet the industry’s evolving needs,” said Ankur Gupta, senior vice president and general manager, DDCP, Siemens Digital Industries Software. “As semiconductor design is scaling from simple 2D into full 3D IC architectures, test cost savings will be applicable in each chiplet as well as the entire 3D IC package.”

“High-Bandwidth IJTAG innovatively leverages the SSN bus architecture, and delivers patterns much faster than traditional serial methods, leading to substantial reduction in test application time, especially for BIST & Mixed Signal IP testing,” said Srinivas Vooka, Senior Engineering Manager, Google.