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Beyond Design: The Fundamental Structure of Spectral Integrity

Impedance can be characterized in both the time and frequency domains. In the time domain, it influences how electromagnetic energy propagates through interconnects, affecting signal integrity and waveform fidelity. In the frequency domain, AC impedance determines how well the network can suppress noise and deliver clean power at a range of frequencies. AC impedance shapes how power rails respond to transient loads. Impedance becomes a filter; high impedance at certain frequencies can cause resonances, while low impedance can suppress noise. Maintaining AC impedance within acceptable limits across the entire bandwidth is essential to minimize unwanted radiation and ensure compliance with electromagnetic compatibility standards.

Traditionally, there was a belief that placing a few decoupling capacitors near each IC power pin was sufficient to stabilize voltage at the device, an approach that proved effective at lower frequencies. In the time domain, these capacitors act as local energy reservoirs, delivering charge to the load during transient events until the power supply can respond. However, in the frequency domain, decoupling capacitors distributed strategically across the power distribution network (PDN) serve a complementary role by reducing impedance across a range of frequencies, helping the PDN meet its AC impedance objectives. Thus, decoupling capacitors fulfill two distinct yet interdependent functions—one temporal, one spectral—that together ensure robust power integrity.

The typical PDN topology (Figure 1) consists of numerous connections from the voltage regulator module (VRM), through capacitors, vias, to wide traces and copper pours, power and ground planes to the solder balls and interconnects on the IC silicon itself. The PDN must provide a constant supply voltage, within a tolerance of 5%, at the power pins of each IC. This voltage must be stable from DC up to the maximum bandwidth, which is typically five times the fundamental frequency. At the same time, these connections not only deliver power but also provide the return signal path.

The power distribution network has four major functions:

1. Provides a low-impedance, high-energy supply path to the ICs.
2. Reduces noise on the power supply at the IC die. 
3. Minimizes ground bounce—common-mode potential between the IC die and the return path.
4. Reduces electromagnetic radiation from the board’s fringing fields.

Inductance is the curse of high-speed design. At DC and low frequencies, inductance is negligible and can often be disregarded. However, as signal frequencies and edge rates rise, the limitations of multilayer PCBs become increasingly apparent. Parasitic capacitance and inductance begin to dominate, undermining the most fundamental design assumptions. Among these, inductance plays a particularly critical role, affecting nearly every aspect of signal and power integrity, from transient response to impedance control and EMI susceptibility.

As signal frequencies and edge rates increase, the AC impedance of the PDN rises, primarily due to the inductance associated with bypass and decoupling capacitors connected to the power and ground planes. Each capacitor inherently includes an equivalent series inductance (ESL), which causes its impedance to climb at higher frequencies.

Capacitors exhibit their lowest impedance at their self-resonant frequency (Figure 2), which is governed by the interplay of capacitance, equivalent series resistance (ESR), and equivalent series inductance (ESL). To meet the PDN’s target impedance at a specific frequency, a capacitor is selected such that, once mounted on the PCB, it resonates at that frequency and presents an impedance equal to its ESR. Placing multiple capacitors in parallel reduces their combined ESR, allowing the aggregate impedance to approach the desired target level. Moreover, the inductance introduced by the capacitor’s mounting configuration significantly influences circuit behavior. It arises from three key contributors:

1. The capacitor footprint.
2. Its vertical placement relative to the reference plane.
3. The spreading inductance of the power plane.

Together, these elements define the loop geometry. Larger loop areas result in higher inductance. Among these, the footprint (land pattern) has the greatest influence on the capacitor’s equivalent series inductance (ESL). It encompasses via placement relative to the pad, the dimensions of the connecting traces, and the configuration of vias linking to the power and ground planes. The position of these planes within the PCB stackup determines via length, which directly affects inductance. For high-layer-count stackups, place decoupling capacitors on the same side of the board as the IC to minimize via length and loop area. Since inductance is proportional to the magnetic field generated by the loop, reducing loop energy by tightening the geometry lowers overall inductance.

Bulk bypass capacitors are effective up to approximately 10 MHz, offering low impedance in that range (Figure 3). For higher frequencies, ceramic capacitors extend decoupling performance into the hundreds of megahertz. Beyond this, only on-die capacitance and the intrinsic planar capacitance between tightly coupled power and ground planes can effectively suppress PDN impedance.

This inter-plane capacitance acts as an ideal high-frequency capacitor, free from lead loop inductance and exhibiting minimal equivalent series resistance (ESR), making it highly effective at mitigating noise in the gigahertz range. Achieving tight coupling—typically less than 5 mils—between these planes significantly enhances this capacitance, providing a robust high-frequency energy reservoir.

While signal trace lengths are often meticulously matched, the return current path is frequently overlooked, yet it plays a critical role in timing and signal integrity. Any delay in the return displacement current path, such as detouring around the plane gap, can introduce skew between timing-critical signals.

The return current path also plays a pivotal role in power integrity. Discontinuities and high-impedance paths, such as splits in ground or power planes, poor return path geometry, and insufficient return vias, can severely impact signal integrity and power delivery in high-speed designs. These issues increase loop inductance, degrade decoupling capacitor effectiveness, and allow high-frequency transients to propagate, resulting in voltage drops, ground bounce, EMI, crosstalk, and common mode radiation.

The primary aim in designing a high-performance power distribution network is to suppress impedance peaks below the target threshold and shift resonant frequency components beyond the signal bandwidth. Achieving this requires strategic mitigation of cavity resonances and electromagnetic emissions.

Key Design Strategies for AC Impedance Optimization

• Minimize Cavity Impedance With Thin Dielectrics

Using a thin dielectric layer between power and ground planes is one of the most effective methods for damping modal resonances. It lowers spreading inductance, reduces cavity impedance, and attenuates high-frequency peaks. A smaller plane separation also reduces the equivalent magnetic current area at the plane edges, thereby shrinking the local fringing field volume and minimizing emissions for a given field strength.

• Select High-Dk Dielectrics for Enhanced Planar Capacitance

Contrary to conventional high-speed design practices that favor low-Dk materials, the interplane dielectric should have a high dielectric constant (Dk) to increase planar capacitance. Since this dielectric lies between planes and has a minimal influence on signal propagation, you can optimize it independently for power integrity.

• Elevate Resonant Frequencies via Geometry and Stitching

To push parallel cavity resonances above the signal bandwidth, reduce the plane dimensions, and incorporate stitching vias between similar planes. These vias disrupt standing wave patterns and help suppress localized resonances.

• Suppress Edge-fired Emissions With Plane Offset Techniques

Resonant emissions typically originate from fringing fields at board edges. While reducing plane separation is effective for ground/power pairs, it’s not always feasible for multilayer stacks. An alternative is to shrink power planes slightly (~200 mil) relative to ground planes. This shifts the fringing field inward, reducing edge radiation and improving EMC performance. Dampening resonance with R-C terminators may also improve plane resonance.

Spectral integrity is established through the precise control of frequency-domain behavior across a system’s signal paths. Its structure is built on a combination of physical layout, material properties, and electromagnetic design principles. At its core are transmission line geometries that preserve waveform fidelity, dielectric materials that maintain consistent impedance across frequencies, and return path continuity that minimizes mode conversion and radiated emissions. Decoupling strategies, PDN resonance control, and stackup symmetry all contribute to a stable spectral profile. When these elements are harmonized, the system maintains clean spectral content—minimizing distortion, reflections, and noise coupling—ensuring reliable performance in high-speed digital and mixed-signal environments.

Key Points

• Maintaining AC impedance within acceptable limits across the entire bandwidth is essential to minimize unwanted radiation and ensure compliance with EMC standards.
• Decoupling capacitors fulfill two distinct yet interdependent functions—one temporal, one spectral—that together ensure robust power integrity.
• At DC and low frequencies, inductance is negligible and can often be disregarded. However, as signal frequencies and edge rates rise, parasitic capacitance and inductance begin to dominate.
• Each capacitor includes an equivalent series inductance (ESL), which causes its impedance to climb at higher frequencies.
• Capacitors exhibit their lowest impedance at their self-resonant frequency.
• The inductance introduced by the capacitor’s mounting configuration significantly influences circuit behavior.
• For high-layer-count stackups, it’s optimal to place decoupling capacitors on the same side of the board as the IC, minimizing via length and loop area.
• Beyond a few hundred megahertz, only on-die capacitance and the intrinsic planar capacitance between tightly coupled power and ground planes can effectively suppress PDN impedance.
• The return current path plays a pivotal role in power integrity. Discontinuities and high-impedance paths can severely impact signal integrity and power delivery in high-speed designs.

Resources

Beyond Design by Barry Olney: “The Impact of PDN Impedance on EMI,” “The Curse of the Golden Board,” “The Target Impedance Approach to PDN Design.”

This column originally appeared in the October 2025 issue of Design007 Magazine.