Setting the Standards for AI-era Packaging: Key Takeaways from IMPACT 2025

Estimated reading time: 3 minutes

Discussions on component-to-system-level integration took center stage at the International Microsystems, Packaging, Assembly and Circuits Technology (IMPACT) 2025, Asia-Pacific’s leading conference for microsystems, packaging, and circuit technology, which celebrated its 20th year in October.

Co-organized and supported by the Global Electronics Association, the event in Taipei, Taiwan, brought global industry leaders together to explore how packaging innovations are shaping the AI era. A special session, titled "Component to System-Level Integration," gathered experts from AMD, ASE, Kinsus, and Wistron to examine how packaging technologies are evolving to meet the growing complexity of AI systems—and why developing shared guidelines and standards has become a pressing priority.

This year’s conference theme, “Energy-Efficient AI: From Cloud to Edge,” reflects how the hardware behind AI is changing. As systems move toward a hybrid cloud-edge model, with edge computing taking on tasks such as real-time processing and inference, the challenge lies in creating high-performance, low-power solutions that can scale across diverse applications.

Semiconductor packaging, once seen primarily as a manufacturing step, has become a critical enabler of system integration and miniaturization. Integrating multiple chips and functions into compact, power-efficient packages and modules for high-performance computing, communication, and power applications demands a coordinated approach across the supply chain. That coordination, however, depends on a shared set of guidelines and standards that are still evolving.

The Component to System-Level Integration session, organized and chaired by the Global Electronics Association, was led by Devan Iyer, chief strategist for advanced electronic packaging. With more than 35 years of experience at Texas Instruments, Amkor, and Infineon Technologies, Iyer opened the discussion by emphasizing that electronic packaging acts as a key enabler at both the component and system levels, and highlighted critical gaps in today’s guidelines and standards.

The presentations underscored the needs, trends, and challenges shaping the future of packaging, as well as possible paths forward. Speakers discussed the need to update existing standards and develop new ones in the context of emerging technologies, covering materials, substrates, and PCBs through design, assembly, and reliability at both the component and system levels.

Highlights included:

• Raja Swaminathan (AMD): Discussed system-level architecture and its role in next-generation AI performance
• C.P. Hung (ASE R&D Center): Explored heterogeneous integration in data center applications
• Dennis Lin (Kinsus): Examined substrate and PCB innovations for chiplet packaging
• Ander Hsieh (Wistron): Shared strategies to improve large BGA assembly reliability

“As AI applications grow explosively, packaging technology has evolved from a supporting role to a critical driver of system performance,” Iyer said. “However, there are opportunities to update existing standards and develop new guidelines and standards at the component, module, and system levels.”

The Global Electronics Association plays a pivotal role in driving the global conversation around advanced electronic packaging. The Association is collaborating with manufacturers, designers, and technology suppliers to define a standardized framework for packaging innovation. The goal goes beyond compliance. It’s about establishing a common technical language that enables efficient collaboration, shortens development cycles, and reduces duplication across the supply chain.

The conversations at IMPACT 2025 underscored a broader industry shift: advanced electronic packaging is now central to how AI hardware evolves, and the pace of that evolution will depend on how quickly the industry aligns on common standards. By fostering open technical exchange and harmonization, industry groups and technology leaders are laying the foundation for a more connected and agile global supply chain.

As the conference continues alongside the TPCA Show (Oct. 22–24), one message stands out: the next leap in AI performance won’t come from a single innovation—it will come from shared standards that make seamless integration possible at every level of the system.

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Editor's note: Devan Iyer, chief strategist, Advanced Electronics Packaging, Global Electronics Association, also wrote a blog post about the event, titled, "How AI Is Reshaping Electronic Packaging to Advance at the Component and System Level." Read the blog post here.