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Beyond Design: Micro-ohm Power Delivery Network for AI-driven GPUs

The evolution of modern processors, marked by faster edge transitions, reduced output impedance, and increasingly complex bus architectures, has significantly augmented the demands on PCB infrastructure. These challenges are compounded by AI-driven graphics processing units (GPUs), which require exceptionally high-power delivery at ultra-low operating voltages, placing greater stress on power integrity and layout design.

NVIDIA’s H100/H200 GPUs, for instance, consume 700-1000 watts per GPU, with entire training clusters demanding multiple megawatts. To achieve this level of performance, the AC impedance of the system must be maintained in the micro-ohm range. Incorporating robust power-and-ground plane architecture allows designers to ensure stable power delivery, preserve controlled impedance, and enhance electromagnetic interference (EMI) suppression, all while supporting advanced thermal management strategies. These capabilities are critical to achieving the reliability, performance, and scalability demanded by innovative AI systems.

The power and ground planes in a high-speed, multilayer PCB perform seven crucial functions:

1. Allow the routing of controlled impedance transmission lines in both microstrip and stripline configurations.
2. Provide a reference voltage for the exchange of digital signals.
3. Distribute stable power to all logic devices.
4. Suppress crosstalk between switching signals.
5. Provide planar capacitance to decouple high frequencies.
6. Present a shield for electromagnetic radiation on internal layers.
7. Facilitate thermal dissipation of high-power-consuming devices.

For all these reasons, planes are essential in today’s high-speed multilayer PCBs. Unfortunately, the number of power supplies required is increasing dramatically with IC complexity, and accounting for them all has become a real challenge. The high number of supplies leads to higher-layer-count substrates. While in the past, we had more signal routing layers than planes, the opposite is now the case, as the majority of stackup layers are reserved for power distribution. Although this increases cost, it may be a godsend because it segregates critical signals to avoid crosstalk and reduces radiation because of the close coupling of signal traces to the reference planes.

Power planes may be segmented into distinct voltage domains to support various supply rails (as illustrated in Figure 2). However, because digital circuits typically share a common ground reference, there is generally no justification for splitting the ground plane. Instead, routing boundaries or keep-out zones should be used to isolate signal paths and prevent cross-domain interference. Splitting the ground plane introduces impedance discontinuities, increases crosstalk, and exacerbates EMI and should therefore be avoided. Effective mixed-signal design relies on disciplined routing practices. Ground planes should remain continuous but may be logically partitioned, with carefully placed pass-through gaps in the signal layer keep-out regions to allow control signals to enter and exit sensitive zones without compromising signal integrity.

Designing AI-driven GPU systems is an entirely different challenge. Each H100 GPU can consume between 700 and 1,000 watts, necessitating multiplane stackups with heavy, wide power planes and densely packed via arrays. Operating at a core voltage of 0.85V, the power distribution network must maintain micro-ohm-level impedance to ensure stable performance. The PCB layout must accommodate VDD (0.85V), VHBM (1.2V), VDDQ (1.1V), VDDIO (1.8V), and auxiliary power rails (1.8V and 3.3V), each paired with closely coupled ground references for optimal power integrity. These lower core voltages contribute to reduced power consumption and thermal output. However, even minor voltage drops can cause instability.

Signal integrity constraints are equally demanding. Routing for PCIe Gen5 and NVLink (GPU-to-GPU interconnect technology) requires controlled impedance—typically 85Ω differential—along with precise delay matching and isolation from noisy power domains. These high-speed differential pairs must be tuned carefully using stripline or microstrip geometries adjacent to tightly coupled reference planes. To minimize stubs and reflections, designers should employ back-drilled vias, via-in-pad structures, and blind or buried vias throughout the layout.

The multiplane HDI stackup—16–20 layers—typically incorporates fifth-order HDI structures (five sequential layers of microvia technology), embedded capacitance, and multiple tightly coupled ground-power pairs. Dielectric materials in signal layers are chosen for their low loss tangent (Df) and low dielectric constant (Dk) to support high-speed signal integrity. For power delivery, materials with low Df and high Dk are paired with tightly spaced power and ground planes to maximize planar capacitance and improve decoupling performance.

Also, thermal management demands the integration of heat spreaders directly within the PCB layout. Copper pours and multiple thermal vias must be precisely aligned with the GPU die and voltage regulator module (VRM) regions to facilitate efficient heat dissipation. The layout must also accommodate liquid cooling interfaces, including provisions for cold plate mounting, mechanical keep-out zones, and accurate thermal pad placement.

However, the real challenge lies in achieving micro-ohm AC impedance (<1 mΩ) across the power delivery network, especially when conventional high-speed designs typically only reach several milli-ohms at best. This level of performance requires a combination of advanced techniques, including:

This level of performance requires a combination of advanced techniques, including:

1. Large, solid, uninterrupted copper planes: Avoid splits, cutouts, or segmentation. Ensure full-layer copper coverage for the core VDD and GND. This maximizes conductivity and minimizes inductance and resistance.
2. Increase copper thickness: Use 2 oz to 4 oz of copper for power layers. Thicker copper reduces both DC and AC resistance. This is essential for high-energy paths in AI GPU boards.
3. Tight power-ground layer pairing: Place power and ground planes adjacent in the stackup. Use multiple planes in parallel to reduce impedance. Use a high Dk dielectric with thin spacing (e.g., < 3 mils) to increase planar capacitance. This lowers impedance at high frequencies and improves decoupling.
4. Optimize via arrays: Use dense stitching vias between power and ground planes. Employ via-in-pad, back-drilled, and filled vias to reduce inductive effects. This helps maintain low impedance across layers and improves thermal flow.
5. Minimize loop area: Route high-speed signals with tight return paths over ground planes. This reduces loop inductance and EMI and is critical for maintaining signal integrity in high-speed designs.
6. Use multi-phase VRMs: This divides the task of voltage regulation across multiple channels, plus this architecture improves efficiency, thermal performance, and power stability.

Use embedded capacitance materials: Materials such as ZBC2000, 3M ECM, or FaradFlex offer built-in decoupling above 1 GHz. These enhance high-frequency noise suppression without discrete capacitors and support micro-ohm impedance targets in dense multilayer PCBs.

The NVIDIA H100 GPU has substantial high-density on-die capacitance with low impedance pathways, but it is not sufficient on its own to meet the ultra-low impedance demands of the power delivery network, especially under high-frequency switching conditions. Achieving micro-ohm AC impedance, well below the milli-ohm threshold, requires meticulous optimization across the entire power delivery network, including copper geometry, layer stackup, via architecture, low ESL decaps and embedded planar capacitance.

The key to achieving ultra-low impedance lies in implementing multiple parallel power-ground planes and maximizing planar capacitance through tightly spaced power-ground pairs. An additional plane pair in parallel reduces the overall impedance by half and doubles the capacitance available for high-frequency decoupling. Above 1 GHz, this approach becomes critical, as discrete decoupling capacitors introduce lead and loop inductance, limiting their effectiveness in reducing impedance. Such high-frequency performance is vital for AI-driven GPUs, which require exceptionally low impedance to maintain stability and efficiency under demanding workloads.

Key Points

• The AC impedance of the AI-driven GPU systems must be maintained in the micro-ohm range.
• They necessitate multiplane stackups with heavy, wide power planes and densely packed via arrays.
• The high number of supplies leads to higher-layer-count substrates.
• Because digital circuits typically share a common ground reference, there is no justification for splitting the ground plane.
• Splitting the ground plane introduces impedance discontinuities, increases crosstalk, and exacerbates EMI.
• To minimize stubs and reflections, designers should employ back-drilled vias, via-in-pad structures, and blind or buried vias.
• The multiplane HDI stackup typically incorporates 5th-order HDI structures, embedded capacitance, and multiple tightly coupled ground-power pairs.
• Copper pours and multiple thermal vias must be precisely aligned with the GPU die and voltage regulator module (VRM) regions to facilitate efficient heat dissipation.
• The real challenge lies in achieving micro-ohm AC impedance across the power delivery network.

Resources

• Beyond Design by Barry Olney: “PDN Trends and Challenges, Plane Crazy Part 2,” “The Fundamental Rules of High-Speed PCB Design Part 3.”
• Tuning and Deploying a Language Model on NVIDIA H100
• NVIDIA H100 Tensor Core GPU Architecture
• Designing hardware for hosting AI-tailored GPUs

This column originally appeared in the November 2025 issue of Design007 Magazine.