SMTA Announces Wafer-Level Packaging Symposium Program

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The SMTA is excited to announce the technical program for the 2026 Wafer-Level Packaging Symposium. The symposium will be held February 17-19, 2026 at The Hyatt Regency San Francisco Airport in San Francisco, California.

The technical program features two exciting keynote presentations. On Tuesday, February 17, 2026, Ashkan Seyedi, Director, Networking at NVIDIA will present “Pioneering System Integration for Tomorrow's AI Workloads.” On Wednesday, February 18, 2025, Ritesh Jain, Senior Vice President, Engineering & Operations at Lightmatter, will present, “3D Photonic Interposers: Lighting the Path Beyond Moore’s Law.” 

Technical sessions include over 20 expert speakers who delve into Metrology and Characterization, Assembly and Test, Co-Packaged Optics, Flip Chip, Panel Level Packaging and Innovation in Substrates, and more. The program features presentations from leading organizations including National Institute of Standards and Technology, Nhanced Semiconductors, Purdue University, SkyWater Technology, USHIO, and more. 

The symposium concludes with two professional development courses on Thursday, February 19, 2026. The first course, “The Critical Role of PCB Strain Measurement in Ensuring Reliability of Advanced Wafer-Level Packages,” will be instructed by Takahiro James Hara, Kyowa Americas, Inc. Gamal Refai Ahmed, Ph.D., GAMA63, will instruct the second course, “Current and Future Challenges and Solutions in AI & HPC System Thermal Management.” Access to these courses is included in standard registration. 

Registration for this event is open online here. All presentations, professional development courses and events open to attendees are included in registration.