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Suggested Items

DFM Mistakes Designers Make When Moving to ELIC

07/20/2026 | Anaya Vardya, American Standard Circuits
The transition from HDI to every layer interconnect (ELIC) is where the DFM gap between design intent and fabrication reality is most visible. Several common misconceptions appear consistently in the data packages we review at ASC. The most common ELIC design mistake mirrors what we generally see in first-time UHDI builds: using process minimums everywhere because they appear on a capability chart. In ELIC, this is especially consequential. If only one region truly requires aggressive geometry, say, a fine-pitch BGA escape, the rest of the design should preserve margin. Relaxing non-critical areas makes the overall build more manufacturable without sacrificing the dense region that drives the stackup.

Every Layer Interconnect: The Promise, the Pain, and the Practical Limits

07/02/2026 | Anaya Vardya, American Standard Circuits
Every layer interconnect (ELIC) is an architectural statement about how a PCB is built, signaling a fundamental shift in how we think about routing density, vertical interconnect, and the relationship between design and fabrication. To understand what ELIC solves, you have to understand what it replaces. Traditional HDI construction uses a rigid core with sequential build-up layers on one or both sides:configurations such as 2-4-2 or 3-2-3.

Base Material Properties and Microvia Reliability

07/01/2026 | Ed Kelley, Victory Giant Technology
The drive toward higher circuit density is challenging PCB manufacturers and their supply chains alike, with base materials as a critical foundation for complex designs. HDI designs present specific challenges and requirements for these materials, but given the myriad possible designs and applications, there is no optimal “one size fits all” material. Perhaps the most challenging HDI designs are those that use stacked vs. staggered microvias, with the number of layers of stacked microvias and the pitch between them as critical variables.

Target Condition: An Exploration of Flooding PCB Layers

04/02/2026 | Kelly Dack -- Column: Target Condition
The concept of flooding PCB layers with copper has been around for so long, you’d think we’d have it mastered. We haven’t. (Oh, and by “we,” I mean design engineers and the software tools we depend on.) Years ago, PCB artwork was created by hand using light tables, with tape applied to Mylar. Signals were slow, traces were relatively wide, and high-current paths were simply “beefed up” with wider copper. Signal integrity wasn’t yet a driving concern. Today, solid return paths are fundamental to robust design. We understand the importance of continuous reference planes for signal integrity and EMI control.

Happy’s Tech Talk #47: Automation for Complex Multilayer Fabrication Stackups

03/31/2026 | Happy Holden -- Column: Happy’s Tech Talk
Multilayer stackups have evolved dramatically as they’ve been adopted for high-performance computing (HPC) and artificial intelligence (AI) server applications. These high-speed, high I/O designs require the designer and fabricator to manage more boundary conditions than ever before. In practice, the stackup is no longer “just a stackup.” It becomes the foundation for signal integrity, reliability, manufacturability, and cost.
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