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Cadence announced a transformative step forward in redefining how semiconductors are designed with the launch of the ChipStack™ AI Super Agent—an agentic AI solution for front-end silicon design and verification. The Cadence® ChipStack AI Super Agent is the world’s first agentic workflow for automating chip design and verification. It provides up to 10X productivity improvements for coding designs and testbenches, creating test plans, orchestrating regression testing, debugging and automatically fixing issues.
“ChipStack represents a major leap in our design-for-AI and AI-for-design strategy, applying agentic AI directly to our customers’ front-end flows to tackle the growing complexity and scale of modern chips,” said Anirudh Devgan, president and CEO, Cadence. “By leveraging intelligent agents that autonomously call our underlying tools, we are enabling dramatic productivity gains for our customers in critical design and verification tasks while freeing scarce engineering talent to focus on innovation.”
The newly launched ChipStack AI Super Agent exemplifies Cadence’s approach to Intelligent System Design™, where AI orchestration, principled simulation and accelerated computing work seamlessly together to deliver transformative solutions for semiconductor and system innovation. This agentic AI solution orchestrates multiple virtual engineers, all using Cadence’s foundational EDA tools. The technology integrates agentic AI with proven Cadence optimization AI and AI assistant solutions, which have been used in over 1,000 tapeouts to date, including the Verisium™ Verification Platform and Cadence Cerebrus® Intelligent Chip Explorer, as well as Cadence’s JedAI data and AI platform.
The ChipStack AI Super Agent flexibly supports cloud-based and on-premises frontier models, including open NVIDIA Nemotron models that can be customized with NVIDIA NeMo and cloud-hosted models such as OpenAI GPT, to improve designer productivity. This continues the fulfillment of the vision of a true “silicon agent,” spanning the many disciplines and workflows needed to deliver the next generation of intelligent devices.
“Our customers are facing a significant senior deficit in the engineering talent needed to deliver on their product roadmaps,” said Paul Cunningham, vice president and general manager of Research and Development, Cadence. “Our ChipStack AI Super Agent is a game changer for design and verification productivity, and deployments are ramping fast.”
The Cadence ChipStack AI Super Agent is in early deployment with several of the world’s top chip design and system companies, including Altera, NVIDIA, Qualcomm and Tenstorrent, among others.
"The Cadence ChipStack AI Super Agent has significantly reduced our verification effort in some areas by approximately 10X, enabling our team to achieve closure much more swiftly and confidently,” stated Arvind Vidyarthi, senior director of engineering, Altera. “By pairing an interactive, engineer-in-the-loop experience with Cadence’s advanced AI-driven verification technologies, we are realizing step-function productivity gains and achieving deeper functional coverage on our most complex designs.”
“As semiconductor complexity continues to accelerate, AI has become essential to designing the next generation of chips,” said Timothy Costa, GM of Industrial and Computational Engineering, NVIDIA. “Our collaboration with Cadence, including innovations like the ChipStack AI Super Agent, demonstrates how combining intelligent reasoning capabilities such as Mental Models and automated formal test plan generation with NVIDIA accelerated computing can unlock new levels of productivity and efficiency for chip designers.”
“Qualcomm is pleased to collaborate with Cadence on the evaluation of the ChipStack AI Super Agent for a broad user base,” said Paul Penzes, vice president of engineering at Qualcomm. “Early results indicate strong, encouraging performance enhancements, and we look forward to realizing the productivity gains.”
“ChipStack greatly improved the efficiency of our formal verification efforts,” said Daniel Cummings, principal engineer of RISC-V Cores, Tenstorrent. “During a three-month evaluation on three critical design blocks, it reduced verification time by up to 4X. Running the agent on Tenstorrent hardware also demonstrated our ability to deliver the high-performance, on-prem inference needed for production-scale LLM workloads.”
