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Imec, EVG Demo Wafer-to-Wafer Hybrid Bonding at 200nm Pitch with Record Overlay Accuracy

05/28/2026 | PRNewswire
This week, at the 2026 IEEE Electronic Components and Technology Conference (ECTC), imec, a world-leading research and innovation hub in advanced semiconductor technologies, and EV Group (EVG), leading provider of semiconductor manufacturing equipment and process solutions, present a robust and highly yielding wafer-to-wafer hybrid bonding technology at 200nm Cu interconnect pad pitch, demonstrated on a test vehicle with routable interconnects.

Direct Metallization: A Strategic Enabler for Advanced PCB Manufacturing

05/27/2026 | Carmichael Gugliotti, Director, MacDermid Alpha Electronics Solutions
The increasing power and complexity of electronics systems are intensifying the demands on printed circuit boards and IC substrates. Applications that include AI infrastructure, high-performance computing, electric vehicles, and next-generation consumer electronics require higher interconnect density and uncompromising reliability. At the same time, PCB fabricators are navigating a manufacturing environment shaped by supply chain volatility, sustainability mandates, and ongoing cost constraints.

QTREX in Advanced Talks with Top-Five Global Quantum Computing Firm on Strategic Collaboration

05/22/2026 | Globe Newswire
QTREX Quantum Ltd. a developer of additively manufactured electronics (AME) technologies for cryogenic interconnect and quantum hardware infrastructure, announced that it is in advanced discussions with one of the top five companies globally in quantum computing systems regarding a strategic collaboration agreement.

System Architecture Beyond the Die With Advanced Packaging as the Scaling Factor

05/14/2026 | Chetan Arvind Patil, Marvell Technology
In conventional monolithic semiconductor design, system integration was achieved within a single die and constrained by reticle limits. Compute cores, cache, memory controllers, and input output (I/O) interfaces were all co-optimized on a single process node, with performance closely tied to transistor density and on-die interconnect efficiency. This monolithic system-on-chip (SoC) approach enabled low-latency communication and relatively straightforward power delivery. However, as design for compute-intensive SoCs approaches reticle limits and advanced-node costs increase, the ability to continue scaling within a single die begins to diminish.

Webinar Review, Part 2: Building the AI Backbone at IBM on Systems-level Packaging

04/20/2026 | Marcy LaRont, I-Connect007
The second presentation in a recent Global Electronics Association’s Executive Pulse webinar series widened the lens on advanced packaging, moving beyond the component level to a systems-level view of how AI is reshaping the electronics landscape. Building on Dr. Hemanth Dhavaleswarupu of AMD’s previous discussion of chip-level packaging innovation, Dr. Jung Yoon of IBM explored the broader infrastructure implications, from the data center floor to the global supply chain.
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