EDADOC: Building the ‘Neural Hub’ for High-Compute Chips Within a Compact Space

Estimated reading time: 7 minutes

ECIO: In response to these pain points, how does the “design + manufacturing” one-stop model proposed by EDADOC help break through the challenges?

Wang Huidong: Our core advantage lies in breaking down barriers between different stages of the industry chain and achieving full end-to-end collaboration “from requirements to delivery.” This is especially critical for high-complexity products such as ATE test boards.

First, it maximizes collaboration efficiency. Because our design and manufacturing teams operate within the same integrated system, we can conduct process feasibility reviews at the early stages of a project, effectively avoiding design rework. Data shows that this approach shortens the R&D cycle by more than 30% compared with the industry average.

Second, it enables the precise realization of technical specifications. At the design stage, engineers can directly access the factory’s process database, integrating manufacturing requirements—such as impedance control and thick-copper processing—into the design, ensuring a 1:1 realization of the original design intent.

For example, when a leading AI chip company was developing a high-compute chip, the yield of its 48-layer ATE test board once fell below 50%. After our involvement, the design and manufacturing teams worked together. Through 12 rounds of data-driven iteration, we ultimately increased the yield to 92%, while controlling test signal timing skew within 5 ps (picoseconds), enabling the customer to complete mass production validation three months ahead of the schedule. This is the value delivered by full end-to-end collaboration.

ECIO: This case is truly impressive. To support the mass production of such high-complexity products, I assume there have been substantial, targeted investments in hard capabilities such as equipment, processes, and quality control?

Wang Huidong: Yes. To ensure flawless execution from design to finished product, we have made systematic investments across the board.

In terms of equipment, we have introduced high-precision CCD drilling machines, Mitsubishi laser drilling systems, Lauffer multilayer lamination production lines, and Keysight impedance testers, among other advanced equipment. We are now capable of manufacturing ultra-high-layer PCBs with more than 120 layers, achieving ±0.01 mm accuracy in thick-copper trace control and impedance accuracy of ±5%.

On the process side, we have established a dedicated process database for special materials, developing proprietary workflows specifically for high-speed substrates. This addresses long-standing industry challenges such as uneven lamination and warpage, resulting in standardized and repeatable process paths.

For quality control, we have built a full end-to-end quality assurance system, with strict checks at every stage from raw material intake to final product testing. We have also introduced AI-based visual inspection systems, increasing defect detection accuracy to over 99.8%. Through these investments, we have achieved stable mass production of high-end ATE test boards with more than 120 layers.

ECIO: Beyond hardware, EDADOC often emphasizes the concept of a data closed loop. How does this help drive yield improvement?

Wang Huidong: Real-time data interoperability between the design side and the manufacturing side is the key to rapid iteration. We have built a complete data closed loop through a “digital platform + standardized processes” approach.

Simply put, the manufacturing side synchronizes material performance data, process deviation data, and yield analysis results to the design side in real time. The design team then uses this data to optimize design rules. Much of the experiential data from manufacturing is ultimately transformed into a “process constraint library” on the design side, enabling front-end design to avoid manufacturability issues at the source. This model has shortened our ATE test board iteration cycle by 40%, and our mass production yield is 15–20% higher than the industry average. This model has shortened our ATE test board iteration cycle by 40%, and our mass production yield is 15%~20% higher than the industry average.

ECIO: With the rise of new advanced packaging technologies such as Chiplet, what changes do you foresee for ATE test boards in the future, and how is Ebo Technology positioning itself?

Wang Huidong: In the chiplet era, ATE test boards are facing three major transformations: the modularization of testing requirements, higher-density signal transmission, and the standardization of interface protocols.

This requires test boards to adopt a “multi-interface, composable” design that supports higher-density I/O interfaces while remaining compatible with industry-standard protocols. In response to these changes, EDADOC has already taken proactive steps: We have established a dedicated chiplet test technology task force to conduct in-depth research on modular testing solutions; we collaborate with partners across the industry value chain to participate in the development of interface standards; and we continue to optimize our design tools and process flows. At present, we have completed the prototype development of multiple chiplet test boards.

At EDADOC, we deliver more than just hardware; we deliver a commitment. We will continue to embrace changes and help our customers accelerate time-to-market in the chiplet era.

ECIO: Thank you very much, Mr. Wang, for the wonderful presentation. It has given us a much clearer understanding of the technical depth of ATE test boards and EDADOC’s approach to breaking through industry challenges.

Wang Huidong: Thank you.

• < Previous Page