Estimated reading time: 5 minutes

Beyond Design: Skip-layer Routing—The Waveguide Structure That Makes 224G Possible

As data rates climb from 112G PAM4 toward 224G PAM4 and beyond, electronics designers are discovering that traditional stripline and microstrip geometries are no longer sufficient. The physics simply break. Rise times are now in the single‑digit picosecond range, loss budgets are measured in millimeters, and even tiny discontinuities can collapse a PAM4 eye.

Next-generation Ethernet is moving to 224G signaling, enabling the transition to 1.6 terabit Ethernet. As data complexity explodes and servers hit their physical density limits, the industry can no longer rely on simply adding more pluggable modules. The only viable path forward is faster SerDes, which converts parallel data into a high-speed serial stream for transmission and reconstructs the parallel data at the receiver. Beyond raw bandwidth, 224G delivers architectural advantages: fewer cables, fewer switches, and more efficient network fabrics. Its inherent backward compatibility ensures that operators can integrate 224G into existing Ethernet environments without disruption.

Higher data rates demand modulation schemes with greater spectral efficiency. For decades, non-return-to-zero (NRZ) has been the workhorse for standards like PCIe and Ethernet 802.3, but as bit rates surpassed 32 Gbps, PAM4 signaling has become the standard. This scheme uses multiple signal levels or phases to encode more bits per symbol, thereby increasing the channel's spectral efficiency and data rate. However, they also increase the complexity and sensitivity of the signal-processing and recovery circuits, requiring careful PCB design to ensure proper signal quality and synchronization.

NRZ is a modulation technique that has two voltage levels to represent logic 0 and logic 1 and is limited to 28 Gbs per lane. PAM4 uses four voltage levels to represent the 2-bit logic combinations 11, 10, 01, and 00 (Figure 1). A 224G PAM4 lane requires approximately 56 GHz of usable channel bandwidth.

To survive at these speeds, routing must evolve from controlled impedance traces into engineered electromagnetic structures. One of the most promising of these structures is skip‑layer routing, a differential waveguide geometry originally developed for IC substrates now emerging as a practical solution for ultra high speed PCB channels. It involves a type of substrate-integrated waveguide structure for differential pairs. A differential stripline pair is essentially routed between two reference planes and surrounded with a fence of ground vias. This creates a differential coaxial-like waveguide within the substrate, commonly used to carry high-speed signals down to the BGA ball-out.

The limitation is bandwidth; PAM4 requires 56 GHz. At these frequencies:

• Traditional stripline excites higher-order modes
• Vias behave like resonant cavities
• Plane cavities radiate
• Crosstalk becomes unavoidable
• Copper roughness dominates loss
• Dielectric loss is no longer the limiting factor

The channel must keep the signal in the quasi-TEM mode. That is the clean, single-mode behavior where the fields stay tightly contained between the trace and its reference planes. Once a higher-order mode is triggered and the fields disperse, the fields spill into lossy paths, the waveform distorts, and the eye collapses.

This is where skip-layer routing comes into play. It is a coaxial-like waveguide formed by a differential pair sandwiched between two reference planes and surrounded by a via fence. This creates a rectangular cavity that behaves like a differential waveguide (Figure 2). The waveguide geometry pushes the first higher-order mode far above the operating frequency.

The cutoff is determined by the cavity width, height, via spacing, and trace separation. The via pitch must be ≤ λ/8 (0.37 mm) at the highest frequency. If the cutoff is above 56 GHz, the channel remains clean with reduced EMI, minimal differential to common-mode conversion, and low lane-to-lane crosstalk.

Also, at 56 GHz for 112G PAM4 and 112 GHz for 224G PAM4, conductor loss becomes the dominant impairment in the channel. Rough copper dramatically increases skin-effect loss, introduces phase-delay variation, and drives additional mode conversion, all of which collapse PAM4 eye height. Using hyper-very-low-profile (HVLP) copper mitigates these effects, reducing conductor loss by roughly 1–2 dB per inch at 56 GHz compared to standard copper, a substantial improvement at these frequencies.

Skip-layer routing uses blind skip-vias to jump directly to the appropriate stripline layer, eliminating unnecessary layer transitions, via stubs, antipad discontinuities, and reference plane changes. Skip-layer routing aligns perfectly with the emerging rules for ultra-high-speed stackups:

1. Thin dielectrics (2–3 mil). Thin dielectrics confine the fields and raise the cutoff frequency.
2. Ultra-low loss materials. The waveguide reduces radiation and crosstalk, but dielectric loss still matters.
3. HDI-only via structures. Through-vias excite higher-order modes. Skip-vias and microvias do not.
4. Minimize transitions. Skip-layer routing reduces the number of via transitions dramatically.
5. Field containment is mandatory. Skip-layer routing is literally a field containment structure.
6. Crosstalk must be engineered. The via fence becomes the crosstalk control mechanism.

Suitable Dielectrics for 224G
For 224G PAM4, only ultra-low-loss dielectrics with Df = 0.002 and tightly controlled Dk (3.2–3.4) are suitable. These materials use E-glass spread fiber to reduce skew and must support 56 GHz Nyquist bandwidth while minimizing loss, skew, and higher-order mode excitation.

Stackups Where Skip-layer Is Mandatory

1.  112G short-reach hybrid stackup. A short-reach hybrid stackup is a mixed-performance PCB structure designed to support 112G PAM4 on selected layers while keeping overall fabrication cost and layer count under control. It blends:

• One or two ultra-low-loss stripline layers for the SerDes lanes
• Standard low-loss or mid-loss materials (e.g., Isola 370HR) for the rest of the board
• HDI microvias and skip-vias for clean BGA escape
• Conventional through-vias for slower signals and power distribution

A 112G short-reach hybrid stackup (chip-to-chip) is shown in Figure 3. It uses blind skip-vias from layers 1 to 3 to give a clean escape from the fine-pitch BGA, with the 112G lanes routed on layer 3 using Megtron 7, while medium-speed digital signals run on layer 5 in 370HR to reduce cost. The iCD Stackup Planner is set to HDI sequential-build mode to exclude resin flow.

The 224G long-reach ultra-low-loss stackup (backplanes, etc.) in Figure 4 supports dual 224G waveguide layers on L3 and L5. Surface skip-layer vias drop directly into each waveguide layer, preserving quasi-TEM behavior, cutting transitions, and driving loss down. GND via fences are used to close the cavity. This is the architecture Intel and Synopsys are converging toward.

Figure 5 illustrates numerous differential pair grounded coplanar waveguides routed internally on the stripline layers. Via fences shield the pairs as they traverse the board to the RF connectors.

Skip-layer routing is not a fad, but a necessary evolution of PCB interconnects as we push toward 224G and beyond. It brings packaging-level electromagnetic engineering into the PCB domain, giving designers a practical way to maintain quasi-TEM propagation, suppress higher-order modes, and control crosstalk at frequencies where traditional stripline fails. As data rates double, the PCB will increasingly resemble a microwave structure, and skip-layer routing is one of the first signs of that future.

Key Points

• Next-generation Ethernet is moving to 224G signaling, enabling the transition to 1.6 terabit Ethernet.
• Higher data rates demand modulation schemes with greater spectral efficiency.
• As bit rates surpassed 32 Gbps, PAM4 signaling has become the standard.
• At these speeds, routing must evolve from controlled impedance traces into engineered electromagnetic structures.
• Skip-layer routing is a coaxial-like waveguide formed by a differential pair sandwiched between two reference planes and surrounded by a via fence.
• The via pitch must be ≤ λ/8 (0.37 mm) at the highest frequency.
• Rough copper dramatically increases skin-effect loss, introduces phase-delay variation, and drives additional mode conversion, all of which collapse PAM4 eye height.
• Skip-layer routing uses blind skip-vias to jump directly to the appropriate stripline layer, eliminating unnecessary layer transitions, via stubs, antipad discontinuities and reference plane changes.
• For 224G PAM4, only ultra low loss dielectrics with Df = 0.002 and tightly controlled Dk (3.2–3.4) are suitable.

Resources

• Beyond Design by Barry Olney: Balancing Trade-Offs for Optimal PCB Design, Substrate Integrated Waveguides
• Skip-Layer Routing for High Bandwidth Channels, Interference Technology
• Will Skip-Layer Routing Work Past 56 GHz?
• Accelerating Hyperscale Data Centers w/ 224G SerDes Ethernet, Synopsys Blog
• 224G Ethernet PHY IP, Synopsys
• 224 Gbps PAM4 end‑to‑end channel solutions, Intel

This column originally appeared in the June 2026 issue of I-Connect007 Magazine.