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Siemens announced that it has entered into an agreement to acquire Defacto Technologies, a privately held EDA software company active in the register-transfer level (RTL) design field focused on automated SoC design creation and integration.

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DFM Mistakes Designers Make When Moving to ELIC

07/20/2026 | Anaya Vardya, American Standard Circuits
The transition from HDI to every layer interconnect (ELIC) is where the DFM gap between design intent and fabrication reality is most visible. Several common misconceptions appear consistently in the data packages we review at ASC. The most common ELIC design mistake mirrors what we generally see in first-time UHDI builds: using process minimums everywhere because they appear on a capability chart. In ELIC, this is especially consequential. If only one region truly requires aggressive geometry, say, a fine-pitch BGA escape, the rest of the design should preserve margin. Relaxing non-critical areas makes the overall build more manufacturable without sacrificing the dense region that drives the stackup.
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