Defense Speak Interpreted: Will Defense Become a Totally New Supplier for Drone Electronics?
The Right Approach: The End of an Era—DoD Proposes MIL-PRF-31032 Cancellation
According to TrendForce's latest memory industry research, DRAM supply will remain tight through 2027, and uncertainty persists over memory suppliers' HBM4e validation timelines. Together, these constraints are prompting AI chip vendors to scale back the HBM configurations of their next-generation products.
Since the third quarter of 2026, NVIDIA has begun expanding its evaluation of the Rubin Ultra’s HBM configuration beyond its original 12-Hi HBM4e design to include 8-Hi HBM4e, 12-Hi HBM4, and 8-Hi HBM4 alternatives. The final specification has yet to be determined. In addition to NVIDIA, several CSPs are also evaluating lower HBM capacities for their next-gen in-house AI ASICs.
TrendForce notes that recent memory shortages have already led to several adjustments to AI chip memory specifications. For instance, CSPs and server OEMs reduced RDIMM capacities for server configurations during the first half of 2026. More recently, NVIDIA decided to halve the SOCAMM capacity of its next-generation Vera Rubin Superchip modules after determining that LPDDR5X supply constraints are likely to continue through 2027.
NVIDIA maintained 12-Hi HBM4e as the baseline design for the Rubin Ultra from 2025 through the first half of 2026. However, beginning in early 3Q26, the company started evaluating lower-specification alternatives. This change is primarily driven by two supply-side constraints: First, the overall DRAM shortage expected in 2027 will limit the wafer capacity that memory suppliers can allocate to HBM production. Second, there are still uncertainties regarding the validation schedule and production yield ramp-up for 12-Hi HBM4e.
TrendForce notes that NVIDIA’s primary objective for the Rubin Ultra generation is to increase I/O speed, while expanding GPU shipment volume remains a secondary priority. If NVIDIA ultimately decides to scale back its HBM specifications, it is expected to do so by reducing the number of DRAM stack layers.
Ultimately, whether HBM4e completes validation and enters mass production on schedule will determine whether Rubin Ultra's I/O speed can be raised from the previous-generation Rubin's 8–11.7 Gbps to 14–16 Gbps, or whether it will only reach 11–12 Gbps through HBM4 design optimization.
Meanwhile, within a given generation, the number of DRAM stack layers determines the trade-off between HBM capacity per GPU and the number of GPUs that can be shipped.
TrendForce believes the final configuration will also depend on wafer allocation decisions made by memory suppliers. From a supply-demand perspective, HBM bit shipments are projected to grow by 50–60% YoY in 2027, which will still be insufficient to keep pace with demand growth.
TrendForce expects HBM suppliers to retain pricing power throughout 2027 under these supply-constrained conditions, with significant increases in HBM pricing already widely anticipated across the industry. AI chip vendors will therefore face the dual challenge of both limited HBM supply and higher procurement costs, increasing the incentive to adopt lower-capacity HBM configurations.
According to TrendForce's latest memory industry research, DRAM supply will remain tight through 2027, and uncertainty persists over memory suppliers' HBM4e validation timelines. Together, these constraints are prompting AI chip vendors to scale back the HBM configurations of their next-generation products.
Since the third quarter of 2026, NVIDIA has begun expanding its evaluation of the Rubin Ultra’s HBM configuration beyond its original 12-Hi HBM4e design to include 8-Hi HBM4e, 12-Hi HBM4, and 8-Hi HBM4 alternatives. The final specification has yet to be determined. In addition to NVIDIA, several CSPs are also evaluating lower HBM capacities for their next-gen in-house AI ASICs.
TrendForce notes that recent memory shortages have already led to several adjustments to AI chip memory specifications. For instance, CSPs and server OEMs reduced RDIMM capacities for server configurations during the first half of 2026. More recently, NVIDIA decided to halve the SOCAMM capacity of its next-generation Vera Rubin Superchip modules after determining that LPDDR5X supply constraints are likely to continue through 2027.
NVIDIA maintained 12-Hi HBM4e as the baseline design for the Rubin Ultra from 2025 through the first half of 2026. However, beginning in early 3Q26, the company started evaluating lower-specification alternatives. This change is primarily driven by two supply-side constraints: First, the overall DRAM shortage expected in 2027 will limit the wafer capacity that memory suppliers can allocate to HBM production. Second, there are still uncertainties regarding the validation schedule and production yield ramp-up for 12-Hi HBM4e.
TrendForce notes that NVIDIA’s primary objective for the Rubin Ultra generation is to increase I/O speed, while expanding GPU shipment volume remains a secondary priority. If NVIDIA ultimately decides to scale back its HBM specifications, it is expected to do so by reducing the number of DRAM stack layers.
Ultimately, whether HBM4e completes validation and enters mass production on schedule will determine whether Rubin Ultra's I/O speed can be raised from the previous-generation Rubin's 8–11.7 Gbps to 14–16 Gbps, or whether it will only reach 11–12 Gbps through HBM4 design optimization.
Meanwhile, within a given generation, the number of DRAM stack layers determines the trade-off between HBM capacity per GPU and the number of GPUs that can be shipped.
TrendForce believes the final configuration will also depend on wafer allocation decisions made by memory suppliers. From a supply-demand perspective, HBM bit shipments are projected to grow by 50–60% YoY in 2027, which will still be insufficient to keep pace with demand growth.
TrendForce expects HBM suppliers to retain pricing power throughout 2027 under these supply-constrained conditions, with significant increases in HBM pricing already widely anticipated across the industry. AI chip vendors will therefore face the dual challenge of both limited HBM supply and higher procurement costs, increasing the incentive to adopt lower-capacity HBM configurations.
