VeCS HDI Process Technology: Has the Time Come for Broader Adoption?

Estimated reading time: 2 minutes

Editor’s note: Vertical conductive structures (VeCS) is a PCB fabrication approach developed by Joan Tourné, CEO of NextGin Technology. By replacing many of the sequential-build processes associated with stacked microvias, VeCS offers PCB fabricators a potentially simpler manufacturing approach to HDIs. The technology can reduce or eliminate multiple lamination cycles, ease some stackup constraints, and achieve greater vertical interconnect density while leveraging conventional PCB fabrication equipment and processes.

Yet, in some circles, VeCS is controversial. More than five years ago, we took a hard look at VeCS, but in our industry, that is a long time. Every layer interconnect (ELIC) is experiencing broader adoption in HDI builds, but it also carries significant processing and reliability challenges. In this article, Tourné re-examines VeCS, explaining the how and why, and expanding on its pros and cons.

Packaging Trends Driving PCB and Substrate Technology

Packaging technology has always driven the PCB, but today's AI and high-performance computing devices are accelerating that relationship. As compute density, bandwidth, and power requirements increase, package, substrate, and PCB design become more interdependent.

Modern AI processors, such as NVIDIA's Blackwell architecture, require thousands of package connections, support multiple stacks of high-bandwidth memory (HBM), and can dissipate as much as 1,000 watts of power or more. These demands are driving new approaches to package substrates, redistribution layers (RDLs), thermal management, and PCB fabrication, where manufacturing itself is becoming a limiting factor. As bandwidth increases and tolerances tighten, maintaining acceptable production yields with conventional PCB processes becomes more difficult. Testing every high-speed node is both costly and technically demanding, and requires sophisticated equipment and specialized expertise.

For some applications, RDLs with pitches approaching 150 µm and below provide sufficient interconnect density. As previously discussed, technologies such as VeCS are one such approach, as they increase vertical interconnect density while leveraging largely conventional PCB manufacturing processes.

Signal and power performance are the key drivers toward adopting advanced process technologies. As the bandwidth/frequencies climb, building a perfect transmission line is a significant challenge. Not Df and Dk values so much as minimizing reflections and GND return paths—tuning impedances to minimise the reflections from component to component. These optimizations are done in 3D field solvers that address and tune every element in the transmission line: pad sizes, antipads, inductance, capacitive responses, etc.

Ultimately, advanced packaging is no longer simply about connecting silicon to a circuit board. It has become a multidisciplinary optimization exercise that balances electrical performance, mechanical reliability, thermal management, manufacturability, and cost. As system complexity increases, innovations in both packaging and PCB fabrication will play an equally important role in enabling the next generation of electronic systems.

To continue reading this article, which originally appeared in the August 2026 issue of I-Connect007 Magazine, click here.