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Trouble in Your Tank: What Pushed the Tech Envelope in 2012 and a Look at 2013

Editor's Note: This article originally appeared in the December 2012 issue of The PCB Magazine.

Introduction

The three most fundamental metrics of organic interconnections and substrates are imaging feature sizes, hole formation technology and size, and the plating types and thicknesses used for interconnections. These same parameters have been used for nearly four decades to quickly quantify the capability of a fabricator to profitably produce traditional boards. The ability to image conductor lines and, perhaps even more important, the insulating airspace between them, are considered key characteristics. With surface mount components, a dramatic decrease in plated via-hole diameter requirements occurred and, as a result, via holes have become simple vertical interconnections. Now, under competition from laser drilling, both drill bit and machine technology have driven mechanical holes capability much smaller.

Microvia technology appeared in the mid-1990s to allow fine-pitch area array semiconductor packages to be surface mounted. Now, microvia technology is used not only on the surface of the board, but also to interconnect to embedded devices, both formed and inserted, and allow “any layer via” board construction for multilayer applications. The IPC Roadmap identifies where the proficiency within different global locations impacts processing operations. There are not many technical issues between geographies, but they can be significant. Sometimes the technical variation deals with what is more prevalent in portable devices produced around the world [1].

With recent surveys of major PCB fabricators now complete, it is evident that layer counts are rising, board thicknesses increasing and via diameters getting smaller and smaller. PWB complexity and the requirements for increased functionality are pushing the limits of conventional plating processes. This is clearly evident in the areas of solderable finishes, electro-deposition and via-filling technology. There are three crucial process technologies that have gained significant attention in 2012. And it is believed that these processes will take on ever-increasing importance in 2013 and beyond. Of course, there are other important technologies that will also gain further scrutiny in the very near future.  

A Look at 2012

Higher circuit densities, finer pitch, reduced size and improved performance and reliability are major themes for 2012. These themes certainly carry over into 2013 and beyond. RoHS compliance and semiconductor complexity also are prominent drivers going forward. With this as a background, there were three significant game changers for 2012.

Higher Circuit Densities Drive Adoption of HDI

Let’s get this misconception out of the way! HDI and microvia technology are not just for cell phones. HDI is a new way of thinking where electronic interconnects are concerned. Why?  Getting the PCBs to adapt to lead-free assembly processes is increasingly difficult. The thick, high-layer count multilayer boards do not perform well at the higher assembly temperatures. These high-layer count, thick multilayers have through-hole, as well as hand-soldered components and requirements for two or more rework cycles. The higher reflow temperatures and slower wetting of lead-free solders place an enormous strain on the laminate and copper-plated hole barrel. In many cases, the boards cannot be assembled reliably even with newer, higher thermal-performance FR-4s [2].

One solution to this problem is to redesign the multilayer using current design rules and newer innovative fabrication technologies. Microvias offer the most significant opportunity to reduce not only the layers and thicknesses of multilayers, but also their cost while improving their electrical performance and density. Several examples will illustrate these new opportunities. Since blind vias are surface phenomena, to get the maximum benefit from them, layer assignment for signal, ground and power need to be reviewed and alternative constructions considered. These blind vias, by reducing the number of through-holes, contribute to increase routing density that allows the lower layer usage. Finally, by replacing through-hole connectors with surface mount connectors, higher connector density and improved electrical performance can be realized [2].

The resulting new multilayers are not only thinner, less costly and easier to design but are less costly and suitable for lead-free assembly.

What this means from a processing standpoint is that new metalization technologies must be adopted. And these technologies are not all related to electroplating. Some ideas may surprise the reader. Now, let’s look at some of the more significant process technology movements in 2012. Keep in mind that some of these technologies have been in the marketplace for several years. However, these technologies, for some reason, have not seen widespread adoption. That is changing and rapidly.

Copper Super Fill Technology

What began as a means to prevent flux and air entrapment in blind vias has now morphed into  a state of the art process to enable high-density interconnects that go beyond surface blind vias. With the continued need to drive the circuit density higher and higher (and to mininmize layer counts and form factor), copper via fill technology has emerged as a core process for IC substrates and high-reliability, high-density PCBs. Of course, superfilling a blind via is not a simple task. This effort requires that the rate of plating from the capture pad is greater than the rate of deposition on the surface. Otherwise, one will get excessive plating on the surface, further defeating the purpose of HDI. Thus, the term “superfilling” is used.

The fabricator needs to undertand that the plating parameters employed for standard through-hole electrodeposition must be adjusted somewhat to enable super- or bottom-up filling of blind vias.

Some of these adjusted parameters are:

• Increased copper concentration and reduced sulfuric acid levels in plating solution.
• Dual-step cathodic current density ramp (lower current density initially helps with bottom-up fill) and at mid-cycle, increase current density.
• Current density and operating temperature: Low C.D. and low temperature can suppress deposition rate of surface copper and provide suitable replenishment of Cu2+ and brightener to via bottom. In this situation, the filling power is better, but plating efficiency is reduced. (That is why there is a recommendation to bump up current density after initial level).
• Seeder layer (pre-metallization): Before via filling plating, the different seeder layer on microvia will influence the result of filling ability (or dent) and void. A pre-metallization of via filling plating like flash plating 3μm copper thickness will ensure more efficient bottom-up fill especially if direct metallization is used versus conventional electroless copper.
• Equipment type: Via filling plating is very sensitive to equipment set-up, so care should be taken: (1) Use of soluble anode, dissolution of anode may result in side reaction with additives. (2) Use of insoluble anode, the electrolysis reaction of water generates large quantities of oxygen, which can result in excess consumption of organic additives and opposing plating of interface. (3) The agitation set-up of equipment should be stable and uniform. Unsuitable agitation results in decreased filling power and poor plating appearance (surface has directional flow of excess additive adsorption). 
• Control of the organic additives and especially the breakdown products of the additives must be closely monitored and controlled. 

Once these key process parameters are implemented, it is very possible to superfill small diameter blind vias approaching 1:1 aspect ratios (Figure 1).

Figure 1: Copper superfilled and stacked blind vias.

What successful fabricators have learned along the way is that electodeposition of copper is a core competence that must be exploited. The firms that are on the leading edge of interconnect technology have made investments in new plating technology. This investment includes adoption of PPR-periodic pulse reverse plating and additional capabilities for copper super fill.

Solid Post or Paste Interconnect

A second interesting technology that is gaining ground in the market is solid copper or paste interconnect. The readers may be aware of the ALIVH (any layer interstitial via hole) process. A schematic of the ALIVH process is shown in Figure 2. The ALIVH was developed and commercialized by Panasonic [3].

Figure 2: Schematic of the ALIVH process flow [3, 4].

Any-Layer HDI derived from ALIVH is a multilayer resin board that was developed and commercialized by Panasonic, which also created the world's first full-layer IVH structure. This circuit design was incorporated into a mobile phone, which was the first in the industry to weigh 100g or less and have a volume of 100cc or less. Since then, ALIVH applications have expanded from Japanese mobile phones to overseas mobile phones. As of the end of March 2011, more than four hundred million mobile phones incorporating Panasonic ALIVH boards have been shipped globally (source: Panasonic). Now, the ALIVH process has evolved and expanded into many other applications other than the mobile phone market.

To further validate this type of technology, Ormet Circuits has developed and is marketing sintering pastes designed to fill microvias and through-holes. These pastes will thus form a solid post interconnect for ALIVH type HDI structures. An example of a circuit built with Ormet sintering paste is shown in Figure 3.

Figure 3: Via fill with copper sintering paste.  

Solderable Finishes: Paradigm Shift?

This year could be considered the year of the final finish paradigm shift. With RoHS compliance and lead-free assembly taking a huge step to the forefront, continued concerns over long-term reliability and the quality of the final finish are ever more closely related. And to further complicate matters, gold prices have reached as high as US $1,700.00 per troy ounce. Thus, the cost of electroless nickel immersion gold as a solderable finish has greatly impacted end users globally. While potentially reducing the gold thickness is the short-term answer, a long-term solution is to adopt a finish that maintains robust solderability, passes creep corrosion tests and provides highly reliable solder joints for lead-free assembly. One such finish, like a phoenix, has risen from the ashes. That born-again finish is direct electroless palladium over bare copper.

This is an autocatalytic system designed primarily for multiple assembly cycles while promoting long-term solder joint reliability. It should be emphasized that this process is a single metal over bare copper. While not wanting to denigrate ENIG, the author wishes to emphasize the simplicity of direct palladium as the more efficient and cost-effective alternative to ENIG.

Direct palladium over copper provides several benefits:

• Process deposits a pure palladium deposit;
• Short plating cycle (12-14 minutes);
• Deposit of 3-5 µin of pure palladium;
• Withstands multiple lead-free thermal cycles;
• Conductive finish allows for ICT; and
• Solder joint reliability equal to OSP and better than other commercial final finishes.

The intermetallic formed after reflow shows a uniform structure that gives excellent solder joint reliability and strength. Figure 4 represents the intermetallic formed after reflow and a thermal cycling program. For the thermal cycling protocol, the parts were subjected to 1000 cycles at the temperature extremes of -40°C to +125°C for 1000 cycles with 30 minutes dwell time per temperature extreme.

Figure 4: SEM of the solder joint formed after reflow and 1,000 thermal cycles, SAC 305 alloy. Note uniform intermetallic.

While the bulk of the deposited palladium is dissolved into the solder, there remains a small amount of the metal that agglomerates at the tin-copper intermetallic. The dispersion is quite uniform as can be seen in the elemental dot map (Figure 5).

Figure 5: Dot map of elements after reflow and 1,000 thermal cycles. Red dots represent palladium, blue is tin. Yellow is the copper base.  

The direct palladium process has performed well with respect to long-term reliability. The results from ball shear testing of direct palladium along with OSP, ENEPIG and ENIG are shown in Figure 6 [5]. Additional information can be found in the paper referenced here.

Figure 6:  Results of ball shear testing after 3X lead-free reflow cycles.

A Look Ahead to 2013

While 2012 was not the most exciting year with respect to business growth in the printed circuit industry, the respite gave time for industry players to look carefully at enabling and evolutionary technologies. These new ideas, as they gain traction, will permit fabricators to jump up the technology curve (especially with respect to HDI), reduce its dependence on gold metal costs and enable new circuit board designs for many applications.  

While the industry will continue in the coming years to evaluate and implement game-changing technologies, it is only fitting that copper superfilling, paste interconnect and alternative solderable finishes such as direct palladium over copper will gain further traction in 2013 and beyond.

References:

1. IPC Technology Roadmap, 2011.2. Holden, Happy, “Lowering Layers w/HDI for RoHS Robustness,” internal correspondence with author.3. http://industrial.panasonic.com.4. Dietz, Karl. Tech Talk, “Fine Lines and High Yield,” CircuiTree Magazine, May, 2006.5. Trainor, James, “Electroless Palladium as a PCB Finish: The Re-Introduction,” Presented at SMTAI Forth Worth, Texas, 2011. 

Michael Carano is with OMG Electronic Chemicals (formerly Electrochemicals), a developer and provider of processes and materials for the electronics industry supply chain. He has been involved in the PWB, general metal finishing photovoltaic industries for nearly 30 years. Carano holds nine U.S. patents in topics including plating, metallization processes and PWB fabrication techniques.